CS42L52 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CS42L52' PDF : 82 Pages View PDF
5/13/08
CS42L52
changes, the level-controlled output may not always be the same but will always fall within the
thresholds.
Referenced Control Register Location
PGAxVOL[5:0
MAX[2:0], MIN[2:0]
“PGAx Vol. & ALCx Transition Ctl.: ALC, PGA A (Address 12h) & ALC, PGA B (Address 13h)” on page 55
“ALC Threshold (Address 2Ch)” on page 68
Input (before ALC )
M IN [2:0]
below full scale
M A X [2:0 ]
below full scale
ALC
Response
PG A G ain and/or
A tte n u a to r
O u tp u t
(after ALC)
M IN [2:0]
below full scale
M A X [2 :0]
below full scale
RRATE [5:0]
Figure 8. ALC
A R A T E [5:0
]
4.2.3
Noise Gate
The noise gate may be used to mute signal levels that fall below a programmable threshold. This prevents
the ALC from applying gain to noise. A programmable delay may be used to set the minimum time before
the noise gate attacks the signal.
Note: Maximum noise gate attenuation levels will depend on the gain applied in either the PGA or MIC
pre-amplifier. For example: If both +32 dB pre-amplification and +12 dB programmable gain is applied,
the maximum attenuation that the noise gate achieves will be 52 dB (-96 + 32 + 12) below full-scale.
Referenced Control Register Location
Noise Gate Controls............ “Noise Gate Control (Address 2Dh)” on page 69
Output
(dB)
NGEN=1
-52 dB
NGEN=0
-64 dB
-80 dB
Input (dB)
-96
-40
THRESH[2:0]
Figure 9. Noise Gate Attenuation
28
DS680F1
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