CS42L56 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CS42L56' PDF : 92 Pages View PDF
MCLK (MHz)
24.0000
(MKPREDIV=1b)
(MCLKDIV2=1b)
12.0000
(MKPREDIV=0b)
(MCLKDIV2=1b)
6.0000
(MKPREDIV=0b)
(MCLKDIV2=0b)
24.5760
(MKPREDIV=1b)
(MCLKDIV2=1b)
12.2880
(MKPREDIV=0b)
(MCLKDIV2=1b)
6.1440
(MKPREDIV=0b)
(MCLKDIV2=0b)
LRCK (kHz)
8.0000
11.0294
12.0000
16.0000
22.0588
24.0000
32.0000
44.1180
48.0000
8.0000
11.0294
12.0000
16.0000
22.0588
24.0000
32.0000
44.1180
48.0000
8.0000
11.0294
12.0000
16.0000
22.0588
24.0000
32.0000
44.1180
48.0000
8.0000
12.0000
16.0000
24.0000
32.0000
48.0000
8.0000
12.0000
16.0000
24.0000
32.0000
48.0000
8.0000
12.0000
16.0000
24.0000
32.0000
48.0000
MCLK/ LRCK
Clock Ratio
3000
2176
2000
1500
1088
1000
750
544
500
1500
1088
1000
750
544
500
375
272
250
750
544
500
375
272
250
187.5
136
125
3072
2048
1536
1024
768
512
1536
1024
768
512
384
256
768
512
384
256
192
128
SCLK (MHz)
0.496
0.75
0.744
0.992
1.500
1.488
1.984
3.000
2.976
0.496
0.75
0.744
0.992
1.500
1.488
1.984
3.000
2.976
0.496
0.75
0.744
0.992
1.500
1.488
1.984
3.000
2.976
0.512
0.768
1.024
1.536
2.048
3.072
0.512
0.768
1.024
1.536
2.048
3.072
0.512
0.768
1.024
1.536
2.048
3.072
MCLK/SCLK
Clock Ratio
~48
32
~32
~24
16
~16
~12
8
~8
~24
16
~16
~12
8
~8
~6
4
~4
~12
8
~8
~6
4
~4
~3
2
~2
48
32
24
16
12
8
24
16
12
8
6
4
12
8
6
4
3
2
Table 3. Serial Port Clock Ratio Settings (Continued)
CS42L56
RATIO[4:0]
11101
11011
11001
10101
10011
10001
01101
01011
01001
11101
11011
11001
10101
10011
10001
01101
01011
01001
11101
11011
11001
10101
10011
10001
01101
01011
01001
11100
11000
10100
10000
01100
01000
11100
11000
10100
10000
01100
01000
11100
11000
10100
10000
01100
01000
DS851F2
47
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