CS4350 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CS4350' PDF : 39 Pages View PDF
CS4350
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT
Inputs: Logic 0 = GND; Logic 1 = VLC; CL = 20 pF.
Parameter
CCLK Clock Frequency
RST Rising Edge to CS Falling
CCLK Edge to CS Falling (Note 12)
CS High Time Between Transmissions
CS Falling to CCLK Edge
CCLK Low Time
CCLK High Time
CDIN to CCLK Rising Setup Time
CCLK Rising to DATA Hold Time (Note 13)
Rise Time of CCLK and CDIN (Note 14)
Fall Time of CCLK and CDIN (Note 14)
Transition Time from CCLK to CDOUT Valid (Note 15)
Time from CS rising to CDOUT High-Z
Symbol
fsclk
tsrs
tspi
tcsh
tcss
tscl
tsch
tdsu
tdh
tr2
tf2
tscdov
tcscdo
Min
-
500
500
1.0
20
66
66
40
15
-
-
-
-
Max
6
-
-
-
-
-
-
-
-
100
100
100
100
Unit
MHz
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes: 12. tspi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times.
13. Data must be held for sufficient time to bridge the transition time of CCLK.
14. For FSCK < 1 MHz.
15. CDOUT should not be sampled during this time.
RST
t srs
CS
CCLK
CDIN
CDOUT
t spi t css
t scl t sch
t r2
t f2
t csh
t dsu t dh
H i-Im p e da n ce
t scdov
t scdov
t cscdo
Figure 9. Control Port Timing - SPI Mode
DS691F1
15
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