CS4365-EQZ View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CS4365-EQZ' PDF : 51 Pages View PDF
5.13 PCM Clock Mode (address 16h)
7
Reserved
0
6
Reserved
0
5
MCLKDIV
0
4
Reserved
0
3
Reserved
0
2
Reserved
0
1
Reserved
0
CS4365
0
Reserved
0
5.13.1 Master Clock DIVIDE by 2 ENABLE (mclkdiv)
Function:
When set to 1, the MCLKDIV bit enables a circuit which divides the externally applied MCLK signal by 2
prior to all other internal circuitry.
When set to 0 (default), MCLK is unchanged.
44
DS670PP1
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