CS4384-CQZ View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CS4384-CQZ' PDF : 50 Pages View PDF
5.4.6
CS4384
DSD Phase Modulation Mode Enable (DSD_PM_EN)
Function:
When set to 1, DSD phase modulation input mode is enabled and the DSD_PM_MODE bit should be set
accordingly.
When set to 0 (default), this function is disabled (DSD normal mode).
5.5 Filter Control (address 05h)
7
Reserved
0
6
Reserved
0
5
Reserved
0
4
Reserved
0
3
Reserved
0
2
Reserved
0
1
Reserved
0
0
FILT_SEL
0
5.5.1
Interpolation Filter Select (FILT_SEL)
Function:
When set to 0 (default), the Interpolation Filter has a fast roll off.
When set to 1, the Interpolation Filter has a slow roll off.
The specifications for each filter can be found in the Analog characteristics table, and response plots can
be found in Figures 26 to 49.
5.6 Invert Control (address 06h)
7
INV_B4
0
6
INV_A4
0
5
INV_B3
0
4
INV_A3
0
3
INV_B2
0
2
INV_A2
0
1
INV_B1
0
0
INV_A1
0
5.6.1
Invert Signal Polarity (INV_xx)
Function:
When set to 1, this bit inverts the signal polarity of channel xx.
When set to 0 (default), this function is disabled.
5.7 Group Control (address 07h)
7
Reserved
0
6
MUTEC
0
5
Reserved
0
4
P1_A=B
0
3
P2_A=B
0
2
P3_A=B
0
1
P4_A=B
0
0
SNGLVOL
0
5.7.1
38
Mutec Pin Control (MUTEC)
Default = 0
0 - Two Mute control signals
1 - Single mute control signal on MUTEC1
Function:
Selects how the internal mute signals are routed to the MUTEC1 and MUTEC234 pins. When set to ‘0’,
a logical AND of DAC pair 1 mute control signals are output on MUTEC1 and a logical AND of the mute
control signals of DAC pairs 2, 3, and 4 are output on MUTEC234. When set to ‘1’, a logical AND of all
DAC pair mute control signals is output on the MUTEC1 pin, MUTEC234 will remain static. For more in-
formation on the use of the mute control function see the MUTEC1 and MUTEC234 pins in Section 3.11.
DS620A1
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