CS4385-DQZR View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CS4385-DQZR' PDF : 55 Pages View PDF
6.12 PCM Clock Mode (address 16h)
7
Reserved
0
6
Reserved
0
5
MCLKDIV
0
4
Reserved
0
3
Reserved
0
2
Reserved
0
1
Reserved
0
CS4385
0
Reserved
0
6.12.1 Master Clock DIVIDE by 2 ENABLE (MCLKDIV)
Function:
When set to 1, the MCLKDIV bit enables a circuit which divides the externally applied MCLK signal by 2
prior to all other internal circuitry.
When set to 0 (default), MCLK is unchanged.
DS671F2
47
Share Link: 
