CS4396-KS View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CS4396-KS' PDF : 28 Pages View PDF
CS4396
4.0 PIN DESCRIPTION
Reset
RST
See Description
M4(AD0/CS)
See Description M3(AD1/CDIN)
See Description M2(SCL/CCLK)
See Description M0(SDA/CDOUT)
Digital Ground
DGND
Digital Power
VD
Digital Power
VD
Digital Ground
DGND
Master Clock
MCLK
Serial Clock
SCLK
Left/Right Clock
LRCK
Serial Data
SDATA
See Description
M1
1 28
2 27
3 26
4 25
5 24
6 23
7 22
8 21
9 20
10 19
11 18
12 17
13 16
14 15
VREF
FILT+
FILT-
CMOUT
AOUTL-
AOUTL+
VA
AGND
AOUTR+
AOUTR-
AGND
MUTEC
C/H
MUTE
Voltage Reference
Reference Filter
Reference Ground
Common ModeS Voltage
Differential Output
Differential Output
Analog Power
Analog Ground
Differential Output
Differential Output
Analog Ground
Mute Control
Control port/Hardware select
Soft Mute
Reset - RST
Pin 1, Input
Function:
The device enters a low power mode and all internal state machines registers are reset when low. When
high, the device will be in a normal operation mode .
RST
0
1
DESCRIPTION
Enabled
Normal operation mode
Digital Ground - DGND
Pins 6 and 9, Inputs
Function:
Digital ground reference.
Digital Power - VD
Pins 7 and 8, Input
Function:
Digital power supply. Typically 5.0 to 3.0 VDC.
Master Clock - MCLK
Pin 10, Input
Function:
The master clock frequency must be either 256x, 384x, 512x or 768x the input sample rate in Single
Speed Mode; either 128x, 192x 256x or 384x the input sample rate in Double Speed Mode; or 64x, 96x
128x or 192x the input sample rate in Quad Speed Mode. Tables 4-6 illustrate the standard audio sample
rates and the required master clock frequencies.
14
DS288PP1
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