CS4397-KS View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CS4397-KS' PDF : 36 Pages View PDF
CS4397
5.0 PIN DESCRIPTION - DSD MODE
Refer to PCM mode
RST 1 28 VREF
Refer to PCM mode M4(ADO/CS) 2 27 FILT+
Refer to PCM mode M3(AD1/CDIN) 3 26 FILT-
Refer to PCM mode M2(SCL/CCLK) 4 25 CMOUT
Refer to PCM mode M0(SDA/CDOUT) 5 24 AOUTL-
Refer to PCM mode
DGND 6 23 AOUTL+
Refer to PCM mode
VD 7 22 VA
Refer to PCM mode
VD 8 21 AGND
Refer to PCM mode
DGND 9 20 AOUTR+
Master Clock
MCLK 10 19 AOUTR-
DSD Serial Clock
DSD_SCLK 11 18 AGND
Master Clock Mode
CLKMODE 12 17 MUTEC
Left Channel Data
DSD_L 13 16 C/H
Right Channel Data
DSD_R 14 15 MUTE
Refer to PCM mode
Refer to PCM mode
Refer to PCM mode
Refer to PCM mode
Refer to PCM mode
Refer to PCM mode
Refer to PCM mode
Refer to PCM mode
Refer to PCM mode
Refer to PCM mode
Refer to PCM mode
Refer to PCM mode
Refer to PCM mode
Refer to PCM mode
Master Clock - MCLK
Pin 10, Input
Function:
The master clock frequency must be either 4x or 6x the DSD data rate for 64x oversampled DSD data
and 2x or 3x the DSD data rate for 128x oversampled DSD data, refer to Table 7.
CLKMODE
Pin 12, Input
Function:
This pin determines the allowable Master Clock to DSD data ratio as defined in Table 7.
DSD Over-
64x
Sampling Ratio 128x
CLKMODE
0
1
4x
6x
2x
3x
Table 7. MCLK to DSD Data Rate Clock Ratios
DSD Serial Clock - DSD_SCLK
Pin 11, Input
Function:
Clocks the individual bits of the DSD audio data into the DSD_L and DSD_R pins.
Audio Data - DSD_L and DSD_R
Pins 13 and 14, Inputs
Function:
Direct Stream Digital audio data is clocked into DSD_L and DSD_R via the DSD serial clock.
DS333F1
23
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