CS4397-KSZ View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CS4397-KSZ' PDF : 34 Pages View PDF
CS4397
6.0 PIN DESCRIPTION - 8X INTERPOLATOR MODE
Refer to PCM mode
RST
Refer to PCM mode
M4(AD0/CS)
Refer to PCM mode M3(AD1/CDIN)
Refer to PCM mode M2(SCL/CCLK)
Refer to PCM mode M0(SDA/CDOUT)
Refer to PCM mode
DGND
Refer to PCM mode
VD
Refer to PCM mode
VD
Refer to PCM mode
DGND
Master Clock
MCLK
Bit Clock
BCKI
Word Clock
WCKI
Left Channel Data
DIL
Right Channel Data
DIR
1 28
2 27
3 26
4 25
5 24
6 23
7 22
8 21
9 20
10 19
11 18
12 17
13 16
14 15
VREF
FILT+
FILT-
CMOUT
AOUTL-
AOUTL+
VA
AGND
AOUTR+
AOUTR-
AGND
MUTEC
C/H
MUTE
Refer to PCM mode
Refer to PCM mode
Refer to PCM mode
Refer to PCM mode
Refer to PCM mode
Refer to PCM mode
Refer to PCM mode
Refer to PCM mode
Refer to PCM mode
Refer to PCM mode
Refer to PCM mode
Refer to PCM mode
Refer to PCM mode
Refer to PCM mode
Master Clock - MCLK
Pin 10, Input
Function:
The master clock frequency must be either 32x, 48x, 64x or 96x the input sample rate. Table 8 illustrates
the standard audio sample rates and the required master clock frequencies.
Sample Rate
(kHz)
32 x 8
44.1 x 8
48 x 8
MCLK (MHz)
32x
8.1920
48x
12.2880
64x
16.384
11.2896
12.2880
16.9344
18.4320
22.579
24.576
Table 8. Common Clock Frequencies
96x
24.576
33.869
36.864
Bit Clock - BCKI
Pin 11, Input
Function:
Clocks the individual serial data bits into the DIL and DIR pins. Refer to Figure 33
Word Clock - WCKI
Pin 12, Input
Function:
The word clock determines which channel is currently being input on the serial audio data input, SDATA.
The frequency of the word clock must be at 8x the baseband sample rate. Refer to Figure 33.
Serial Audio Data - DIR and DIL
Pins 12 and 13, Inputs
Function:
Two's complement MSB-first serial data is input on these pins. The data is clocked into DIL and DIR via
the bit clock. Refer to Figure 33.
24
DS333F1
Share Link: 
