CS43L21 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CS43L21' PDF : 63 Pages View PDF
CS43L21
LRCK
SCLK
ts(LK-SK)
//
//
tP
//
//
SDIN
ts(SD-SK)
th
//
MSB
//
MSB-1
Figure 4. Serial Audio Interface Slave Mode Timing
Master Mode (Note 12)
Parameters
Symbol Min
Max Units
Output Sample Rate (LRCK)
All Speed Modes
Fs
-
M------C-----L---K---
Hz
128
LRCK Duty Cycle
SCLK Frequency
SCLK Duty Cycle
LRCK Edge to SDIN MSB Rising Edge
SDIN Setup Time Before SCLK Rising Edge
SDIN Hold Time After SCLK Rising Edge
45
1/tP
-
45
td(MSB)
ts(SD-SK)
20
th
20
55
%
64•Fs
Hz
55
%
52
ns
-
ns
-
ns
10. After powering up the CS43L21, RESET should be held low after the power supplies and clocks are set-
tled.
11. See “Example System Clock Frequencies” on page 57 for typical MCLK frequencies.
12. See “Master” on page 29
LRCK
SCLK
td(MSB)
//
//
tP
//
//
SDIN
ts(SD-SK)
th
//
MSB
//
MSB-1
Figure 5. Serial Audio Interface Master Mode Timing
DS723A1
17
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