CS43L21 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CS43L21' PDF : 63 Pages View PDF
4.4.1
CS43L21
Slave
LRCK and SCLK are inputs in Slave Mode. The speed of the D/A is automatically determined based on
the input MCLK/LRCK ratio when the Auto-Detect function is enabled. Certain input clock ratios will then
require an internal divide-by-two of MCLK* using either the MCLKDIV2 bit or the MCLKDIV2 stand-alone
control pin.
Additional clock ratios are allowed when the Auto-Detect function is disabled; but the appropriate speed
mode must be selected using the SPEED[1:0] bits.
Auto-Detect
QSM
Disabled
(Software
Mode only)
512, 768, 1024, 1536,
2048, 3072
Enabled
1024, 1536, 2048*,
3072*
*MCLKDIV2 must be enabled.
HSM
256, 384, 512, 768,
1024, 1536
512, 768, 1024*, 1536*
SSM
128, 192, 256, 384,
512, 768
256, 384, 512*, 768*
Table 3. MCLK/LRCK Ratios
DSM
128, 192, 256, 384
128, 192, 256*, 384*
4.4.2
Master
LRCK and SCLK are internally derived from the internal MCLK (after the divide, if MCLKDIV2 is enabled).
In Hardware Mode the D/A operates in single-speed only. In Software Mode, the D/A operates in either
quarter-, half-, single- or double-speed depending on the setting of the SPEED[1:0] bits.
MCLK
÷1
0
÷2
1
÷ 128
Double
Speed
00
÷ 128
Single
Speed
01
÷ 256
Half
Speed
10
÷ 512
Quarter
Speed
11
LRCK Output
(Equal to Fs)
SPEED[1:0]
MCLKDIV2
÷2
Double
Speed
00
÷2
Single
Speed
01
÷4
Half
Speed
10
÷8
Quarter
Speed
11
SCLK Output
Figure 12. Master Mode Timing
DS723A1
29
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