CS43L21 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CS43L21' PDF : 63 Pages View PDF
CS43L21
6.8 Beep Frequency & Timing Configuration (Address 12h)
7
FREQ3
6
FREQ2
5
FREQ1
4
FREQ0
3
ONTIME3
2
ONTIME2
1
ONTIME1
0
ONTIME0
Note: The DATA_SEL[1:0] bits in reg09h must be set to ‘01’b to enable function control in this register.
Beep Frequency (FREQ[3:0])
Default: 0000
FREQ[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Frequency
Fs = 12, 24, 48 or 96
kHz
260.87 Hz
521.74 Hz
585.37 Hz
666.67 Hz
705.88 Hz
774.19 Hz
888.89 Hz
1000.00 Hz
1043.48 Hz
1200.00 Hz
1333.33 Hz
1411.76 Hz
1600.00 Hz
1714.29 Hz
2000.00 Hz
2181.82 Hz
Pitch
C4
C5
D5
E5
F5
G5
A5
B5
C6
D6
E6
F6
G6
A6
B6
C7
Function:
The frequency of the beep signal can be adjusted from 260.87 Hz to 2181.82 Hz. Beep frequency will scale
directly with sample rate, Fs, but is fixed at the nominal Fs within each speed mode. Refer to Figure 10 on
page 26 for single, multiple and continuous beep configurations using the REPEAT and BEEP bits.
Beep On Time Duration (ONTIME[3:0])
Default: 0000
TIME[3:0]
0000
···
1111
Function:
On Time
Fs = 12, 24, 48 or 96 kHz
86 ms
···
5.2 s
The on-duration of the beep signal can be adjusted from approximately 86 ms to 5.2 s. The on-duration will
scale inversely with sample rate, Fs, but is fixed at the nominal Fs within each speed mode. Refer to Figure
10 on page 26 for single-, multiple- and continuous-beep configurations using the REPEAT and BEEP bits.
DS723A1
45
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