CS43L21-DNZR View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CS43L21-DNZR' PDF : 63 Pages View PDF
4.4.3
CS43L21
High-Impedance Digital Output
The serial port may be placed on a clock/data bus that allows multiple masters for the SCLK/LRCK I/O
without the need for external buffers. The 3ST_SP bit places the internal buffers for these I/O in a high-
impedance state, allowing another device to transmit clocks without bus contention.
CS42L51
Transmitting Device #1
3ST_SP
SCLK/LRCK
Transmitting Device #2
Receiving Device
Figure 13. Tri-State SCLK/LRCK
4.4.4
Quarter- and Half-Speed Mode
Quarter-Speed Mode (QSM) and Half-Speed Mode (HSM) allow lower sample rates while maintaining a
relatively flat noise floor in the typical audio band of 20 Hz - 20 kHz. Single-Speed Mode (SSM) will allow
lower frequency sample rates; however, the DAC's noise floor, that normally rises out-of-band, will scale
with the lower sample rate and begin to rise within the audio band. QSM and HSM corrects for most of
this scaling, effectively increasing the dynamic range of the CODEC at lower sample rates, relative to
SSM.
4.5 Digital Interface Formats
The serial port operates in standard I²S, Left-Justified or Right-Justifieddigital interface formats with varying
bit depths from 16 to 24. Data is clocked into the DAC on the rising edge of SCLK. Figures 14-17 illustrate
the general structure of each format. Refer to “Switching Specifications - Serial Port” on page 16 for exact
timing relationship between clocks and data.
Software
Control: “Interface Control (Address 04h)” on page 41.
Hardware
Control:
Pin
“I²S/LJ” pin 3
Setting
LO
HI
Selection
Left-Justified Interface
I²S Interface
LRCK
SCLK
Left Channel
Right Channel
SDIN
MSB
LSB
MSB
LSB
AOUTA / AINxA
AOUTB / AINxB
Figure 14. I²S Format
MSB
30
DS723A1
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