CS43L21-DNZR View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CS43L21-DNZR' PDF : 63 Pages View PDF
CS43L21
Function:
Divides the input MCLK by 2 prior to all internal circuitry. This bit is ignored when the AUTO bit is disabled
in Slave Mode.
6.4 Interface Control (Address 04h)
7
Reserved
6
5
4
M/S
DAC_DIF2 DAC_DIF1
Master/Slave Mode (M/S)
Default: 0
0 - Slave
1 - Master
3
DAC_DIF0
2
Reserved
1
Reserved
0
Reserved
Function:
Selects either master or slave operation for the serial port.
DAC Digital Interface Format (DAC_DIF[2:0])
Default = 000
DAC_DIF[2:0]
000
001
010
011
100
101
110
100
Description
Left-Justified, up to 24-bit data
I²S, up to 24-bit data
Right-Justified, 24-bit data
Right-Justified, 20-bit data
Right-Justified, 18-bit data
Right-Justified, 16-bit data
Reserved
Reserved
Figure
15 on page 31
14 on page 30
17 on page 3217 on page 32
17 on page 3217 on page 32
17 on page 3217 on page 32
17 on page 3217 on page 32
-
-
Function:
Selects the digital interface format used for the data in on SDIN. The required relationship between the
Left/Right clock, serial clock and serial data is defined by the Digital Interface Format and the options are
detailed in the section “Digital Interface Formats” on page 30.
6.5 DAC Output Control (Address 08h)
7
HP_GAIN2
6
HP_GAIN1
5
HP_GAIN0
4
DAC_
SNGVOL
3
INV_PCMB
2
1
0
INV_PCMA DACB_MUTE DACA_MUTE
Headphone Analog Gain (HP_GAIN[2:0])
Default: 011
HP_GAIN[2:0]
000
001
010
011
100
101
110
111
Gain Setting
0.3959
0.4571
0.5111
0.6047
0.7099
0.8399
1.0000
1.1430
DS723A1
41
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