CS43L22 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CS43L22' PDF : 66 Pages View PDF
Confidential Draft
3/4/10
CS43L22
MCLK
(MHz)
27.0000
Sample Rate,
Fs (kHz)
8.0000
12.0000
24.0000
32.0000
*44.1176...
48.0000
*11.0294...
*22.0588...
16.0000
SPEED[1:0]
(AUTO=’0’b)
11
11
10
01
01
01
11
10
10
32kGROUP
1
0
0
1
0
0
0
0
1
VIDEOCLK
1
1
1
1
1
1
1
1
1
RATIO[1:0]
01
01
01
01
11
01
11
11
01
MCLKDIV2
0
0
0
0
0
0
0
0
0
Note:
*The marked sample rate values are not exact representations of the actual frame clock frequency
They have been truncated to 4 decimal places. The exact value can be calculated by dividing the
MCLK being used by the desired MCLK/LRCK ratio.
Table 1. Serial Port Clocking
4.7 Digital Interface Formats
The serial port operates in standard I²S, Left-Justified, Right-Justified, or DSP Mode digital interface formats
with varying bit depths from 16 to 24. Data is clocked into the DAC on the rising edge of SCLK.
LRCK
SCLK
SDIN
MSB
Left Channel
Right Channel
LSB
MSB
LSB
AOUTA
AOUTB
Figure 12. I²S Format
MSB
LRCK
SCLK
MSB
SDIN
Left Channel
Right Channel
AOUTA
LSB
MSB
AOUTB
Figure 13. Left-Justified Format
LSB
MSB
LRCK
SCLK
SDIN
Left C ha nnel
Right C han nel
MSB
LSB
AOUTA
Audio Word Length (AWL)
Figure 14. Right-Justified Format\
MSB
AOUTB
LS B
30
DS792F2
Share Link: 
