CS43L43 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CS43L43' PDF : 36 Pages View PDF
CS43L43
SWITCHING CHARACTERISTICS - INTERNAL SERIAL CLOCK (Inputs: Logic “0” =
GND, Logic “1” = VL.)
Internal SCLK Mode
LRCK Duty Cycle
SCLK Period
Parameters
SCLK rising to LRCK edge
SDATA valid to SCLK rising setup time
Symbol Min
Typ
(Note 6)
tsclkw
tsclkr
tsdlrs
-
-------1---------
SCLK
-
(---5---1----21---)---F----s- + 10
50
-
t---s---c----l-k----w---
2
-
Max Units
-
%
-
s
-
s
-
ns
SCLK rising to SDATA hold time
Single-Speed Mode tsdh
----------1----------- + 15
-
( 512 ) F s
Double-Speed Mode tsdh
-
----------1----------- + 15
( 384 ) F s
-
ns
-
ns
Notes: 6. In Internal SCLK Mode, the LRCK duty cycle must be 50% +/− 1/2 MCLK Period.
LRCK
SDATA
t sclkr
t s d lrs t s d h
t sclkw
*IN TE R N A L
SCLK
Figure 20. Internal Serial
Mode Input Timing
*The SCLK pulses shown are internal to the CS43L43.
LRCK
MCLK
1
N
N
2
*INTERNAL SCLK
SDATA
Figure 21. Internal Serial Clock Generation
* The SCLK pulses shown are internal to the CS43L43.
N equals MCLK divided by SCLK
DS479PP3
31
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