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CS44600-DQZR View Datasheet(PDF) - Cirrus Logic

Part Name
Description
MFG CO.
CS44600-DQZR
Cirrus-Logic
Cirrus Logic Cirrus-Logic
'CS44600-DQZR' PDF : 76 Pages View PDF
CS44600
7. REGISTER DESCRIPTION
All registers are read/write except for I.D. and Revision Register, Interrupt Status and Decimator OutD registers
which are read only. See the following bit definition tables for bit assignment information. The default state of each
bit after a power-up sequence or reset is listed in each bit description.
7.1 Memory Address Pointer (MAP)
Not a register
7
INCR
6
MAP6
5
MAP5
4
MAP4
3
MAP3
2
MAP2
1
MAP1
0
MAP0
7.1.1
Increment (INCR)
Default = 1
Function:
memory address pointer auto increment control
– 0 - MAP is not incremented automatically.
– 1 - Internal MAP is automatically incremented after each read or write.
7.1.2
Memory Address Pointer (MAPx)
Default = 0000001
Function:
Memory address pointer (MAP). Sets the register address that will be read or written by the control port.
7.2 CS44600 I.D. and Revision Register (address 01h) (Read Only)
7
CHIP_ID3
6
CHIP_ID2
5
CHIP_ID1
4
CHIP_ID0
3
REV_ID3
2
REV_ID2
1
REV_ID1
0
REV_ID0
7.2.1
Chip I.D. (Chip_IDx)
Default = 1101
Function:
I.D. code for the CS44600. Permanently set to 1101.
7.2.2
Chip Revision (Rev_IDx)
Default = 0001
Function:
CS44600 revision level. Revision A is coded as 0001.
48
DS633F1
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