CS4525
2.1 Digital I/O Pin Characteristics
The logic level for each input is set by its corresponding power supply and should not exceed the maximum ratings.
Power Pin Pin Name
I/O
Supply Number
Software Mode
Driver
VD
1
INT
Output
2.5 V-5.0 V, Open Drain
2
SCL
Input
-
3
SDA
Input/Output
2.5 V-5.0 V, Open Drain
7
HP_DETECT
Input
-
MUTE
Input
-
41 DLY_SDOUT Output
2.5 V-5.0 V, CMOS
42
DLY_SDIN
Input
-
EX_TWR
Input
-
43 AUX_SDOUT Output
2.5 V-5.0 V, CMOS
44
AUX_SCLK
Output
2.5 V-5.0 V, CMOS
45
AUX_LRCK
Output
2.5 V-5.0 V, CMOS
Hardware Mode
VD
1
SEL_OSC0
Input
-
2
SEL_OSC1
Input
-
3
ADC/SP
Input
-
7
MUTE
Input
-
41
TWR
Output
2.5 V-5.0 V, Open Drain
42
ERRUVTE
Output
2.5 V-5.0 V, Open Drain
43
ERROC
Output
2.5 V-5.0 V, Open Drain
44
EN_TFB
Input
-
45
I²S/LJ
Input
-
All Modes
VD
4
LRCK
Input
-
5
SCLK
Input
-
6
SDIN
Input
-
8
RST
Input
-
9
LVD
Input
-
46
SYS_CLK Input/Output
2.5 V-5.0 V, CMOS
VD_REG
PWM_SIG1
Output
2.5 V, CMOS
PWM_SIG2
Output
2.5 V, CMOS
VP
OUT1-OUT4 Output
10.5 V-18.0 V Power MOSFET
Table 1. I/O Power Rails
Receiver
2.5 V-5.0 V, with Hysteresis
2.5 V-5.0 V, with Hysteresis
2.5 V-5.0 V
2.5 V-5.0 V
-
2.5 V-5.0 V
2.5 V-5.0 V
-
-
-
2.5 V-5.0 V
2.5 V-5.0 V
2.5 V-5.0 V
2.5 V-5.0 V
-
-
-
2.5 V-5.0 V
2.5 V-5.0 V
2.5 V-5.0 V
2.5 V-5.0 V
2.5 V-5.0 V
2.5 V-5.0 V
2.5 V-5.0 V
2.5 V-5.0 V
-
-
-
12
DS726A1