CS51311 View Datasheet(PDF) - ON Semiconductor
Part Name
Description
MFG CO.
'CS51311' PDF : 21 Pages View PDF
CS51311
Channel 1 − Regulator Output Voltage (1.0 V/div)
Channel 2 − Inductor Switching Node (5.0 V/div)
Channel 3 − VCC (10 V/div)
Channel 4 − Regulator Input Voltage (5.0 V/div)
Figure 11. Pulse−By−Pulse Regulation During Soft
Start (2.0 ms/div)
If the voltage across the Current Sense resistor generates a
voltage difference between the VFB and VOUT pins that
exceeds the OVC Comparator Offset Voltage (86 mV typical),
the Fault latch is set. This causes the COMP pin to be quickly
discharged, turning off GATE(H) and the upper NFET since
the voltage on the COMP pin is now less than the 1.1 V PWM
comparator offset. The Fault latch is reset when the voltage on
the COMP decreases below the discharge threshold voltage
(0.25 V typical). The COMP capacitor will again begin to
charge, and when it exceeds the 1.1 V PWM comparator offset,
the regulator output will Soft Start normally (see Figure 12).
Channel 1 − Regulator Output Voltage (1.0 V/div)
Channel 2 − COMP Pin (1.0 V/div)
Channel 3 − VCC (10 V/div)
Channel 4 − Regulator Input Voltage (5.0 V/div)
Figure 12. Startup with COMP Pre−Charge to 2.0 V
(2.0 ms/div)
Because the start−up circuit depends on the current sense
function, a current sense resistor should always be used.
When driving large capacitive loads, the COMP must
charge slowly enough to avoid tripping the CS51311
overcurrent protection. The following equation can be used
to ensure unconditional startup:
ICHG
CCOMP
t
ILIM * ILOAD
COUT
where:
ICHG = COMP Source Current (30 μA typical);
CCOMP = COMP Capacitor value (0.1 μF typical);
ILIM = Current Limit Threshold;
ILOAD = Load Current during startup;
COUT = Total Output Capacitance.
Normal Operation
During normal operation, Switch Off−Time is constant
and set by the COFF capacitor. Switch On−Time is adjusted
by the V2 Control loop to maintain regulation. This results
in changes in regulator switching frequency, duty cycle, and
output ripple in response to changes in load and line. Output
voltage ripple will be determined by inductor ripple current
and the ESR of the output capacitors
Transient Response
The CS51311 V2 Control Loop’s 200 ns reaction time
provides unprecedented transient response to changes in
input voltage or output current. Pulse−by−pulse adjustment
of duty cycle is provided to quickly ramp the inductor
current to the required level. Since the inductor current
cannot be changed instantaneously, regulation is maintained
by the output capacitor(s) during the time required to slew
the inductor current.
Overall load transient response is further improved
through a feature called “Adaptive Voltage Positioning”.
This technique pre−positions the output capacitors voltage
to reduce total output voltage excursions during changes in
load.
Holding tolerance to 1.0% allows the error amplifiers
reference voltage to be targeted +25 mV high without
compromising DC accuracy. A “Droop Resistor,”
implemented through a PC board trace, connects the Error
Amps feedback pin (VFB) to the output capacitors and load
and carries the output current. With no load, there is no DC
drop across this resistor, producing an output voltage
tracking the Error amps, including the +25 mV offset. When
the full load current is delivered, a 50 mV drop is developed
across this resistor. This results in output voltage being
offset −25 mV low.
The result of Adaptive Voltage Positioning is that
additional margin is provided for a load transient before
reaching the output voltage specification limits. When load
current suddenly increases from its minimum level, the
output capacitor is pre−positioned +25 mV. Conversely,
when load current suddenly decreases from its maximum
level, the output capacitor is pre−positioned −25 mV. For
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