CS5132H View Datasheet(PDF) - ON Semiconductor
Part Name
Description
MFG CO.
'CS5132H' PDF : 20 Pages View PDF
Application Information: continued
Lower (Synchronous) FET Total Losses = Switch Conduc-
tion Losses + Body Diode Losses:
PFETL(TOTAL) = 1.27W + 0.16W =1.43W.
Calculate Maximum NFET Switch Junction Temperature:
TJ = TA + [(PFETL(TOTAL) ) × ΘJA ],
TJ = 50C + (1.43W) × 40°C/W = 107°C.
where
ID = average drive current;
QGATE(X) = total gate charge for each MOSFET;
FSW1, FSW2 = switching frequencies for the synchronous
and non-synchronous sections respectively.
The power dissipation for the IC when VCC1 = VCC2 =
VCC is:
PD = ICC × VCC + ID × VCC,
Calculate the Gate Driver Losses:
PGATE(L) = Q × VGATE × FSW
= 50nC × 12V × 200KHz = 120mW.
where
ICC = quiescent supply current of the IC (both from VCC1
and VCC2).
For the design example in question,
Step 7: Free Wheeling Schottky Diode (3.3V Output)
The four most application-important characteristics of a
Schottky are:
1. Forward voltage drop;
2. Reverse leakage current;
3. Reverse blocking voltage;
4. Maximum permissible junction temperature.
We calculate the average Schottky current:
IAVG = IOUT × (1−D) = 8Α × 0.34 = 2.72Α.
We select the Motorola MBRD835L rated at 8A, with 35V
DC blocking voltage and 0.51Vforward voltage drop.
Neglecting reverse losses, the power dissipation is due to
the conduction loss only and can be computed as follows:
PSCHOTTKY = VF × IAVG,
where
VF = maximum instantaneous forward voltage;
PSCHOTTKY = 0.51V × 2.72Α = 1.39W.
Calculate maximum Schottky junction temperature:
TJ = TA + [(PSCHOTTKY ) × ΘJA ],
TJ = 50C + (1.39W × 80°C/W) = 161°C.
Proper heatsinking (copper pad under Schottky) will be
required to reduce Schottky TJ below +125°C.
Step 8: IC Power Dissipation
The power dissipation on the IC varies with the MOSFETs
used, VCC and the CS5132H operating frequency. This
power dissipation is typically dominated by the average
gate charge current for the MOSFETs. The average current
is approximately:
ID = (QGATE(H) + QGATE(L)) × FSW1 + QGATE × FSW2,
PD = 19mA × 12V + 0.12W + 0.12W + 0.12W = 0.59W.
The junction temperature of the IC is primarily a function
of the PCB layout, since most of the heat is removed
through the traces connected to the pins of the IC.
“Droop” Resistor for Adaptive Voltage Positioning
and Current Limit
Adaptive voltage positioning is used to help keep the out-
put voltage within specification during load transients. To
implement adaptive voltage positioning a “Droop
Resistor” must be connected between the output inductor
and output capacitors and load. This resistor carries the
full load current and should be chosen so that both DC and
AC tolerance limits are met. An embedded PC trace resis-
tor has the distinct advantage of near zero cost implemen-
tation. However, this droop resistor can vary due to three
reasons: 1) the sheet resistivity variation caused by varia-
tion in the thickness of the PCB layer; 2) the mismatch of
L/W; and 3) temperature variation.
1) Sheet Resistivity
For one ounce copper, the thickness variation is typically
1.26 mil to 1.48 mil. Therefore the error due to sheet resis-
tivity is:
1.48 - 1.26
= ±8%.
1.37
2) Mismatch due to L/W
The variation in L/W is governed by variations due to the
PCB manufacturing process. The error due to L/W mis-
match is typically 1%.
3) Thermal Considerations
Due to I2 × R power losses the surface temperature of the
droop resistor will increase causing the resistance to
increase. Also, the ambient temperature variation will con-
tribute to the increase of the resistance, according to the
formula:
R = R20 [1+ α20(Τ−20)],
15
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