CS5165H View Datasheet(PDF) - ON Semiconductor
Part Name
Description
MFG CO.
'CS5165H' PDF : 21 Pages View PDF
CS5165H
ELECTRICAL CHARACTERISTICS (continued) (0°C < TA < +70°C; 0°C < TJ < +125°C; 8.0 V < VCC < 20 V; 2.8 DAC Code:
(VID4 = VID2 = VID1 = VID0 = 1; VID3 = 0); CGATE(H) and CGATE(L) = 3.3 nF; COFF = 330 pF; CSS = 0.1 μF, unless otherwise specified.)
Characteristic
Test Conditions
Min
Typ
Max
Unit
GATE(H) and GATE(L)
High Voltage at 100 mA
Low Voltage at 100 mA
Measure VCC − GATE
Measure GATE
−
1.2
2.0
V
−
1.0
1.5
V
Rise Time
Fall Time
GATE(H) to GATE(L) Delay
GATE(L) to GATE(H) Delay
GATE pull−down
1.6 V < GATE < (VCC − 2.5 V), 8 V < VCC < 14 V
−
(VCC − 2.5 V) > GATE > 1.6 V, 8 V < VCC < 14 V
−
GATE(H) < 2.0 V; GATE(L) > 2.0 V,
30
8.0 V < VCC < 14 V
GATE(L) < 2.0 V; GATE(H) > 2.0 V,
30
8.0 V < VCC < 14 V
Resistor to PGND, Note 3
20
40
80
ns
40
80
ns
65
100
ns
65
100
ns
50
115
kΩ
Fault Protection
SS Charge Time
SS Pulse Period
SS Duty Cycle
VFB = 0 V
VFB = 0 V
(Charge Time/Period) × 100
1.6
3.3
5.0
ms
25
100
200
ms
1.0
3.3
6.0
%
SS COMP Clamp Voltage
VFB Low Comparator
PWM Comparator
VFB = 2.7 V; VSS = 0 V
0.50
0.95
1.10
V
Increase VFB till no SS pulsing and normal Off−time
0.9
1.0
1.1
V
Transient Response
Minimum Pulse Width
(Blanking Time)
COFF
Normal Off−Time
Extended Off−Time
Time−Out Timer
VFB = 1.2 to 5.0 V. 500 ns after GATE(H)
−
(after Blanking time) to GATE(H) = (VCC −1.0 V)
to 1.0 V, 8.0 V < VCC < 14 V
Drive VFB. 1.2 to 5.0 V upon GATE(H) rising edge
50
(> VCC − 1.0 V), measure GATE(H) pulse
width, 8.0 V < VCC < 14 V
VFB = 2.7 V
1.0
VSS = VFB = 0 V
5.0
100
150
ns
150
250
ns
1.6
2.3
μs
8.0
12.0
μs
Time−Out Time
Fault Duty Cycle
Enable Input
VFB = 2.7 V, Measure GATE(H) Pulse Width
VFB = 0V
10
30
50
μs
30
50
70
%
ENABLE Threshold
GATE(H) Switching
0.8
1.15
1.30
V
Shutdown delay (Note 3)
ENABLE−to−GATE(H) < 2.0 V
−
3.0
−
μs
Pull−up Current
ENABLE = 0 V
3.0
7.0
15
μA
Pull−up Voltage
No load on ENABLE pin
1.30
1.8
3.0
V
Input Resistance
ENABLE = 5.0 V, R = (5.0 V − VPULLUP)/IENABLE
10
Power Good Output
Low to High Delay
VFB = (0.8 × VDAC) to VDAC
30
High to Low Delay
VFB = VDAC to (0.8 × VDAC)
30
Output Low Voltage
VFB = 2.4 V, IPWRGD = 500 μA
−
Sink Current Limit
VFB = 2.4 V, PWRGD = 1.0 V
0.5
3. Guaranteed by design, not 100% tested in production.
20
50
kΩ
65
110
μs
75
120
μs
0.2
0.3
V
4.0
15.0
mA
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