CS5165HGDWR16 View Datasheet(PDF) - ON Semiconductor
Part Name
Description
MFG CO.
'CS5165HGDWR16' PDF : 21 Pages View PDF
CS5165H
VCORE
15 k R1
+5.0 V
5.0 k
56 k R2
+5.0 V
CS5165H 10 k
PWRGD
10 k
Q1
2N3906
20 k
Q2
2N3904
Q3
2N3906
OVP
10 K
Figure 22. Circuit To Implement A Dedicated OVP
Output Using The CS5165H
Output Enable Circuit
The Enable pin (pin 8) is used to enable or disable the
regulator output voltage, and is consistent with TTL DC
specifications. It is internally pulled−up. If pulled low
(below 0.8 V), the output voltage is disabled. At the same
time the Power Good and Soft Start pins are pulled low, so
that when normal operation resumes power−up of the
CS5165H goes through the Soft Start sequence. Upon
pulling the Enable pin low, the internal IC bias is completely
shut off, resulting in total shutdown of the Controller IC.
Power Good Circuit
The Power Good pin (pin 13) is an open−collector signal
consistent with TTL DC specifications. It is externally
pulled−up, and is pulled low (below 0.3 V) when the
regulator output voltage typically exceeds ± 8.5% of the
nominal output voltage. Maximum output voltage deviation
before Power Good is pulled low is ± 12%.
Trace 2− PWRGD (2.0 V/div.)
Trace 4− VFB (1.0 V/div.)
Figure 24. Power Good Response to an Out of
Regulation Condition
Figure 24 shows the relationship between the regulated
output voltage VFB and the Power Good signal. To prevent
Power Good from interrupting the CPU unnecessarily, the
CS5165H has a built−in delay to prevent noise at the VFB pin
from toggling Power Good. The internal time delay is
designed to take about 75 μs for Power Good to go low and
65 μs for it to recover. This allows the Power Good signal to
be completely insensitive to out of regulation conditions that
are present for a duration less than the built in delay (see
Figure 25).
It is therefore required that the output voltage attains an
out of regulation or in regulation level for at least the built−in
delay time duration before the Power Good signal can
change state.
Trace 2− PWRGD (2.0 V/div.)
Trace 4− VOUT (1.0 V/div.)
Figure 23. PWRGD Signal Becomes Logic High as
VOUT Enters −8.5% of Lower PWRGD Threshold,
VOUT = +2.84 V (DAC = 10111)
Trace 2− PWRGD (2.0 V/div.)
Trace 4− VFB (1.0 V/div.)
Figure 25. Power Good is Insensitive to Out of
Regulation Conditions that are Present for a
Duration Less Than the Built In Delay
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