CS5166GDWR16 View Datasheet(PDF) - ON Semiconductor
Part Name
Description
MFG CO.
'CS5166GDWR16' PDF : 25 Pages View PDF
CS5166
Response
Time
+
1.2
mH
2.8
14.2
V
A
+
6.1
ms
Input and Output Capacitors
These components must be selected and placed carefully
to yield optimal results. Capacitors should be chosen to
provide acceptable ripple on the input supply lines and
regulator output voltage. Key specifications for input
capacitors are their ripple rating, while ESR is important for
output capacitors. For best transient response, a combination
of low value/high frequency and bulk capacitors placed
close to the load will be required.
THERMAL MANAGEMENT
Thermal Considerations for Power
MOSFETs and Diodes
In order to maintain good reliability, the junction
temperature of the semiconductor components should be
kept to a maximum of 150°C or lower. The thermal
impedance (junction to ambient) required to meet this
requirement can be calculated as follows:
Thermal
Impedance
+
TJ(MAX) *
Power
TA
A heatsink may be added to TO−220 components to
reduce their thermal impedance. A number of PC board
layout techniques such as thermal vias and additional copper
foil area can be used to improve the power handling
capability of surface mount components.
EMI Management
As a consequence of large currents being turned on and off
at high frequency, switching regulators generate noise as a
consequence of their normal operation. When designing for
compliance with EMI/EMC regulations, additional
components may be added to reduce noise emissions. These
components are not required for regulator operation and
experimental results may allow them to be eliminated. The
input filter inductor may not be required because bulk filter
and bypass capacitors, as well as other loads located on the
board will tend to reduce regulator di/dt effects on the circuit
board and input power supply. Placement of the power
component to minimize routing distance will also help to
reduce emissions.
2.0 μH
33 Ω
1000 pF
Figure 35. Filter Components
2.0 μH
+
1200 μF × 3.0/16 V
Figure 36. Input Filter
Layout Guidelines
When laying out the CPU buck regulator on a printed
circuit board, the following checklist should be used to
ensure proper operation of the CS5166.
1. Rapid changes in voltage across parasitic capacitors
and abrupt changes in current in parasitic inductors
are major concerns for a good layout.
2. Keep high currents out of sensitive ground
connections. Avoid connecting the IC GND (LGND)
between the source of the lower FET and the input
capacitor GND.
3. Avoid ground loops as they pick up noise. Use star or
single point grounding.
4. For high power buck regulators on double−sided
PCBs a single large ground plane (usually the bottom)
is recommended.
5. Even though double sided PCBs are usually sufficient
for a good layout, four−layer PCBs are the optimum
approach to reducing susceptibility to noise. Use the
two internal layers as the +5.0 V and GND planes, the
top layer for the power connections and component
vias, and the bottom layer for the noise sensitive
traces.
6. Keep the inductor switching node small by placing
the output inductor, switching and synchronous FETs
close together.
7. The FET gate traces to the IC must be as short,
straight, and wide as possible. Ideally, the IC has to be
placed right next to the FETs.
8. Use fewer, but larger output capacitors, keep the
capacitors clustered, and use multiple layer traces
with heavy copper to keep the parasitic resistance
low.
9. Place the switching FET as close to the +5.0 V input
capacitors as possible.
10. Place the output capacitors as close to the load as
possible.
11. Place the VFB filter resistor in series with theVFB pin
(pin 16) right at the pin.
12. Place the VFB filter capacitor right at the VFB pin (pin
16).
13. The “Droop” Resistor (embedded PCB trace) has to
be wide enough to carry the full load current.
14. Place the VCC bypass capacitor as close as possible to
the VCC pin and connect it to the PGND pin of the IC.
Connect the PGND pin directly to the GND plane.
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