CS5372-BS View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CS5372-BS' PDF : 22 Pages View PDF
CS5371/CS5372
INF- _ Fine Inverting Input, pin 3
Fine inverting analog input.
VREF+ _ Positive Voltage Reference Input, pin 5
Input for an external +2.5 V voltage reference relative to VREF-.
VREF- _ Negative Voltage Reference Input, pin 6
This pin must be tied to VA-.
Digital Inputs
MCLK _ Modulator Clock Input, pin 19
A CMOS compatible clock input for the modulator internal master clock, nominally 2.048
MHz with an amplitude equal to the VD digital power supply.
MSYNC _ Modulator Sync Input, pin 20
A low to high transition resets the internal clock phasing of the modulator. This assures the
sampling instant and modulator data output are synchronous to the external system.
OFST _ Offset Mode Select, pin 14
When high, adds approximately +100mV of offset to the analog inputs to guarantee any zero
input ∆−Σ idle tones are removed. When low, no offset is added.
LPWR _ Low Power Mode Select, pin 23
When set high with MCLK operating at 1.024 MHz, modulator power dissipation is reduced to
15 mW per channel.
PWDN _ Power-down Mode, pin 24
When high, the modulator is in power down mode and consumes 1mW. Halting MCLK while
in power down mode reduces modulator power dissipation to 10 µW.
Digital Outputs
MDATA _ Modulator Data Output, pin 21
Modulator data is output as a 1-bit serial data stream at a 512 kHz rate with an MCLK input of
2.048 MHz. Modulator data is output at a 256 kHz rate with an MCLK input of 1.024 MHz.
MFLAG _ Modulator Flag Output, pin 22
A high level output indicates the modulator is unstable due to an over-range on the analog
inputs.
18
DS255PP2
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