CS5373A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CS5373A' PDF : 40 Pages View PDF
CS5373A
DIGITAL CHARACTERISTICS (CONT.)
Parameter
Master Clock Input
MCLK Frequency
MCLK Period
MCLK Duty Cycle
MCLK Rise Time
MCLK Fall Time
MCLK Jitter (In-band or aliased in-band)
MCLK Jitter (Out-of-band)
Master Sync Input
MSYNC Setup Time to MCLK Rising
MSYNC Period
MSYNC Hold Time after MCLK Falling
MSYNC Instant to TDATA Start
MDATA Output
MDATA Output Bit Rate
MDATA Output Bit Period
MDATA Output One’s Density Range
Full-scale Output Code
TDATA Input
TDATA Input Bit Rate
TDATA Input One’s Density Range
TBSGAIN Full-scale Code
TBSGAIN -20 dB Code
Symbol Min
Typ Max
(Note 30) fCLK
-
(Note 30) tmclk
-
(Note 9) MCLKDC
40
(Note 9) tRISE
-
(Note 9) tFALL
-
(Note 9) MCLKIBJ
-
(Note 9) MCLKOBJ
-
2.048
-
488
-
-
60
-
50
-
50
-
300
-
1
(Note 9, 31)
(Note 9, 31)
(Note 9, 31)
(Note 9, 32)
tmss
tmsync
tmsh
ttdata
20
122
-
40
976
-
20
122
-
-
1220
-
(Note 9)
(Note 33)
fmdata
tmdata
MDATOD
MDATFS
-
-
14
0xA2EBE0
512
1953
-
-
-
-
86
0x5D1420
(Note 34)
(Note 9)
(Note 35)
(Note 35)
ftdata
TBSOD
TBSFS
TBS-20dB
-
256
-
25
-
75
-
0x04B8F2
-
-
0x0078E5
-
Unit
MHz
ns
%
ns
ns
ps
ns
ns
ns
ns
ns
kbits/s
ns
%
kbits/s
%
Notes: 30. MCLK is generated by the CS5378 digital filter. If MCLK is disabled, the device automatically enters a
power-down state.
31. MSYNC is generated by the CS5378 digital filter and is latched on MCLK rising edge, synchronization
instant (t0) on next MCLK rising edge.
32. TDATA can be delayed from 0 to 63 full bit periods by the test bit stream generator in the CS5378 digital
filter. The timing diagrams show no TBSDATA delay.
33. Decimated, filtered, and offset-corrected 24-bit output word from the CS5378 digital filter.
34. TDATA is generated by the test bit stream generator in the CS5378 digital filter.
35. TBSGAIN register value in the CS5378 digital filter.
16
DS703F1
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