11. PIN DESCRIPTION
CS5373A
Positive Capacitor Output CAP+ 1
Negative Capacitor Output CAP- 2
Positive Buffered Output BUF+ 3
Negative Buffered Output BUF- 4
Positive High Precision Output OUT+ 5
Negative High Precision Output OUT- 6
Positive Analog Power Supply
VA+ 7
Negative Analog Power Supply
VA- 8
Negative Voltage Reference VREF- 9
Positive Voltage Reference VREF+ 10
Positive Analog Rough Input INR+ 11
Positive Analog Fine Input INF+ 12
Negative Analog Fine Input INF- 13
Negative Analog Rough Input INR- 14
28 GND
System Ground
27 MODE0 Mode Select
26 MODE1 Mode Select
25 MODE2 Mode Select
24 ATT0
Attenuation Range Select
23 ATT1
Attenuation Range Select
22 ATT2
Attenuation Range Select
21 TDATA Test Bit Stream Input
20 VD
Positive Digital Power Supply
19 GND
System Ground
18 MCLK Master Clock Input
17 MSYNC Master Sync Input
16 MDATA Modulator Data Output
15 MFLAG Modulator Over-range Indicator
Pin
Name
Pin # I/O
Pin Description
CAP+,
CAP-
1 O Capacitor connection for internal anti-alias filter.
2
BUF+,
BUF-
3 O Buffered differential analog output.
4
OUT+,
OUT-
5 O Precision differential analog output.
6
VA+,
7
VA-
8
Analog power supply. Refer to the Specified Operating Conditions.
VREF-, 9 I Voltage reference input. Refer to the Specified Operating Conditions.
VREF+ 10
INR+,
INF+
11 I Analog differential rough and fine + inputs. From the + half of the differential anti-alias fil-
12
ter.
INF-,
INR-,
13 I Analog differential rough and fine - inputs. From the - half of the differential anti-alias filter.
14
MFLAG 15 O Amplitude overload indicator flag.
MDATA 16 O Oversampled ∆Σ bit stream conversion output.
MSYNC 17 I Master sync input. Low to high transition resets the internal clock phasing.
MCLK 18 I Master clock input. CMOS compatible clock input.
GND
19
System ground.
VD
20
Digital power supply. Refer to the Specified Operating Conditions.
TDATA 21 I Test Bit Stream input from digital filter TBS generator.
36
DS703F1