CS5376-BS View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CS5376-BS' PDF : 122 Pages View PDF
CS5376
8.1.5 CONFIG Register
Figure 34. Decimation Engine Configuration Register CONFIG
(MSB)23
22
21
20
19
18
17
16
--
--
--
--
--
DFS2
DFS1
DFS0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
1
0
1
15
14
13
12
11
10
9
8
--
WDFS2
WDFS1
WDFS0
--
MCKFS2 MCKFS1 MCKFS0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
1
0
0
7
6
5
4
3
2
1
(LSB)0
--
--
MCKEN2 MCKEN
MDIFS
SBY
BOOT
MSEN
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
0
0
0
0
0
0
0
1
I/O Address: 0x00
--
Not defined;
read as 0
R
Readable
W
Writable
R/W Readable and
Writable
Bits in bottom rows
are reset condition
Bit definitions:
23:19 --
18:16 DFS
[2:0]
reserved
Decimation Engine
Frequency Select
111: reserved
110: 8.192 MHz
101: 4.096 MHz
(default)
100: 2.048 MHz
011: 1.024 MHz
010: 512 kHz
001: 256 kHz
000: 32 kHz
15 --
reserved
7:6 --
reserved
14:12 WDFS
[2:0]
Watchdog Frequency 5
Select
4
111: reserved
110: 8.192 MHz
3
101: 4.096 MHz
100: 2.048 MHz
011: 1.024 MHz
010: 512 kHz
2
001: 256 kHz
000: 32 kHz (default)
11 --
reserved
MCKEN2 MCLK/2 Output Enable
MCKEN MCLK Output Enable
MDIFS
SBY
MDI Frequency Select:
1: 256 kHz
0: 512 kHz (default)
Standby
1: DE in low power, low
frequency mode
0: DE normal operation
10:8 MCKFS MCLK Frequency Select 1
[2:0]
111: reserved
110: reserved
101: 4.096 MHz
0
100: 2.048 MHz
(default)
011: 1.024 MHz
010: 512 kHz
001: reserved
000: reserved
BOOT
MSEN
Boot Source Select
1: Boot from PROM
0: Boot from SPI
MSYNC Enable
1: MSYNC is generated
from SYNC
0: MSYNC remains low
DS256PP1
56
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