CS5378-ISZ View Datasheet(PDF) - Cirrus Logic
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Description
MFG CO.
'CS5378-ISZ' PDF : 88 Pages View PDF
CS5378
6.4 Master Clock Jitter and Skew
Care must be taken to minimize jitter and skew on
the distributed system clock as both parameters af-
fect measurement performance.
Jitter on the input clock causes jitter in the generat-
ed modulator clock, resulting in sample timing er-
rors and increased noise.
Skew between input clocks from node to node cre-
ates a sample timing offset, resulting in systematic
measurement errors in a reconstructed signal.
DS639F2
23
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