CS53L21-CNZ View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CS53L21-CNZ' PDF : 66 Pages View PDF
4.5.1
CS53L21
Slave
LRCK and SCLK are inputs in Slave Mode. The speed of the A/D is automatically determined based on
the input MCLK/LRCK ratio when the Auto-Detect function is enabled. Certain input clock ratios will then
require an internal divide-by-two of MCLK* using either the MCLKDIV2 bit or the MCLKDIV2 stand-alone
control pin.
Additional clock ratios are allowed when the Auto-Detect function is disabled; but the appropriate speed
mode must be selected using the SPEED[1:0] bits.
Auto-Detect
QSM
Disabled
(Software
Mode only)
512, 768, 1024, 1536,
2048, 3072
Enabled
1024, 1536, 2048*,
3072*
*MCLKDIV2 must be enabled.
HSM
256, 384, 512, 768,
1024, 1536
512, 768, 1024*, 1536*
SSM
128, 192, 256, 384,
512, 768
256, 384, 512*, 768*
Table 3. MCLK/LRCK Ratios
DSM
128, 192, 256, 384
128, 192, 256*, 384*
4.5.2
Master
LRCK and SCLK are internally derived from the internal MCLK (after the divide, if MCLKDIV2 is enabled).
In Hardware Mode the A/D operates in single-speed only. In Software Mode, the A/D operates in either
quarter-, half-, single- or double-speed depending on the setting of the SPEED[1:0] bits.
MCLK
÷ 128
Double
Speed
00
÷ 128
Single
Speed
01
÷ 256
Half
Speed
10
LRCK Output
(Equal to Fs)
÷1
0
÷2
1
÷ 512 Quarter 11
Speed
SPEED[1:0]
MCLKDIV2
÷2
Double
Speed
00
÷2
Single
Speed
01
÷4
Half
Speed
10
SCLK Output
÷8
Quarter 11
Speed
Figure 13. Master Mode Timing
30
DS700PP1
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