CS53L32A-BZ View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CS53L32A-BZ' PDF : 40 Pages View PDF
CS53L32A
4.3 POWER-DOWN
I/O and Power Control Register (address 01h)
7
RESERVED
6
BOOST
5
AINMUX1
4
AINMUX0
3
2
RESERVED RESERVED
1
PDN
Access:
R/W in Two Wire Mode and write only in SPI.
0
CP_EN
Default:
1 - Enabled
Function:
The entire device will enter a low-power state whenever this function is activated. The power-down
bit defaults to ‘enabled’ on power-up and must be disabled before normal operation will begin. The
contents of the control registers are retained when this mode is enabled.
PDN
0
1
MODE
Disabled
Enabled
Table 2. Power-Down Enable
4.4 CONTROL PORT ENABLE
I/O and Power Control Register (address 01h)
7
RESERVED
6
BOOST
5
AINMUX1
4
AINMUX0
3
2
RESERVED RESERVED
1
PDN
Access:
R/W in Two Wire Mode and write only in SPI.
0
CP_EN
Default:
0 - Disabled
Function:
The CS53L32A will enter Control Port mode when this bit is enabled. Stand-Alone is the default power
up mode. See Section 6.3, Recommended Power-up Sequence, for more details.
CP_EN
0
1
MODE
Disabled
Enabled
Table 3. Control Port Enable
DS513F1
19
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