CS5422 View Datasheet(PDF) - ON Semiconductor
Part Name
Description
MFG CO.
'CS5422' PDF : 17 Pages View PDF
CS5422
Both logic level and standard FETs can be used.
Voltage applied to the FET gates depends on the
application circuit used. Both upper and lower gate driver
outputs are specified to drive to within 1.5 V of ground when
in the low state and to within 2.0 V of their respective bias
supplies when in the high state. In practice, the FET gates
will be driven rail−to−rail due to overshoot caused by the
capacitive load they present to the controller IC.
Selection of the Switching (Upper) FET
The designer must ensure that the total power dissipation
in the FET switch does not cause the power component’s
junction temperature to exceed 150°C.
The maximum RMS current through the switch can be
determined by the following formula:
ǸƪIL(PEAK)2 ) (IL(PEAK)
) IL(VALLEY)2 D
ƫ IL(VALLEY))
IRMS(H) +
3
where:
IRMS(H) = maximum switching MOSFET RMS current;
IL(PEAK) = inductor peak current;
IL(VALLEY) = inductor valley current;
D = duty cycle.
Once the RMS current through the switch is known, the
switching MOSFET conduction losses can be calculated:
PRMS(H) + IRMS(H)2 RDS(ON)
where:
PRMS(H) = switching MOSFET conduction losses;
IRMS(H) = maximum switching MOSFET RMS current;
RDS(ON) = FET drain−to−source on−resistance
The upper MOSFET switching losses are caused during
MOSFET switch−on and switch−off and can be determined
by using the following formula:
PSWH + PSWH(ON) ) PSWH(OFF)
+ VIN
IOUT (tRISE ) tFALL)
6T
where:
PSWH(ON) = upper MOSFET switch−on losses;
PSWH(OFF) = upper MOSFET switch−off losses;
VIN = input voltage;
IOUT = load current;
tRISE = MOSFET rise time (from FET manufacturer’s
switching characteristics performance curve);
tFALL = MOSFET fall time (from FET manufacturer’s
switching characteristics performance curve);
T = 1/fSW = period.
The total power dissipation in the switching MOSFET can
then be calculated as:
PHFET(TOTAL) + PRMS(H) ) PSWH(ON) ) PSWH(OFF)
where:
PHFET(TOTAL) = total switching (upper) MOSFET losses;
PRMS(H) = upper MOSFET switch conduction Losses;
PSWH(ON) = upper MOSFET switch−on losses;
PSWH(OFF) = upper MOSFET switch−off losses;
Once the total power dissipation in the switching FET is
known, the maximum FET switch junction temperature can
be calculated:
TJ + TA ) [PHFET(TOTAL) RQJA]
where:
TJ = FET junction temperature;
TA = ambient temperature;
PHFET(TOTAL) = total switching (upper) FET losses;
RΘJA = upper FET junction−to−ambient thermal resistance.
Selection of the Synchronous (Lower) FET
The switch conduction losses for the lower FET can be
calculated as follows:
PRMS(L) + IRMS2 RDS(ON)
+ [IOUT Ǹ(1 * D)]2 RDS(ON)
where:
PRMS(L) = lower MOSFET conduction losses;
IOUT = load current;
D = Duty Cycle;
RDS(ON) = lower FET drain−to−source on−resistance.
The synchronous MOSFET has no switching losses,
except for losses in the internal body diode, because it turns
on into near zero voltage conditions. The MOSFET body
diode will conduct during the non−overlap time and the
resulting power dissipation (neglecting reverse recovery
losses) can be calculated as follows:
PSWL + VSD ILOAD non−overlap time fSW
where:
PSWL = lower FET switching losses;
VSD = lower FET source−to−drain voltage;
ILOAD = load current;
Non−overlap time = GATE(L)−to−GATE(H) or
GATE(H)−to−GATE(L) delay (from CS5422 data sheet
Electrical Characteristics section);
fSW = switching frequency.
The total power dissipation in the synchronous (lower)
MOSFET can then be calculated as:
PLFET(TOTAL) + PRMS(L) ) PSWL
where:
PLFET(TOTAL) = Synchronous (lower) FET total losses;
PRMS(L) = Switch Conduction Losses;
PSWL = Switching losses.
Once the total power dissipation in the synchronous FET
is known the maximum FET switch junction temperature
can be calculated:
TJ + TA ) [PLFET(TOTAL) RQJA]
where:
TJ = MOSFET junction temperature;
TA = ambient temperature;
PLFET(TOTAL) = total synchronous (lower) FET losses;
RΘJA = lower FET junction−to−ambient thermal resistance.
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