CS5531 View Datasheet(PDF) - Cirrus Logic
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MFG CO.
'CS5531' PDF : 52 Pages View PDF
CS5531/32/33/34
2.2.5. Reading/Writing On-Chip Registers
The CS5531/32/33/34’s offset, gain, configuration,
and channel-setup registers are readable and writ-
able while the conversion data register is read only.
As shown in Figure 7, to write to a particular regis-
ter the user must transmit the appropriate write
command and then follow that command by 32 bits
of data. For example, to write 0x80000000 (hexa-
decimal) to physical channel one’s gain register,
the user would first transmit the command byte
0x02 (hexadecimal) followed by the data
0x80000000 (hexadecimal). Similarly, to read a
particular register the user must transmit the appro-
priate read command and then acquire the 32 bits of
data. Once a register is written to or read from, the
serial port returns to the command mode.
In addition to accessing the internal registers one at
a time, the gain and offset registers as well as the
channel setup registers can be accessed as arrays
(i.e. the entire register set can be accessed with one
command). In the CS5531/32, there are two gain
and offset registers, and in the CS5533/34, there are
four gain and offset registers. There are four chan-
nel setup registers in all parts. As an example, to
write 0x80000000 (hexadecimal) to all four gain
registers in the CS5533, the user would transmit the
command 0x42 (hexadecimal) followed by four it-
erations of 0x80000000 (hexadecimal), (i.e. 0x42
followed by 0x80000000, 0x80000000,
0x80000000, 0x80000000). The registers are writ-
ten to or read from in sequential order (i.e, 1, fol-
lowed by 2, 3, and 4). Once the registers are written
to or read from, the serial port returns to the com-
mand mode.
2.3. Configuration Register
To ease the architectural design and simplify the
serial interface, the configuration register is thirty-
two bits long, however, only eleven of the thirty
two bits are used. The following sections detail the
bits in the configuration register.
2.3.1. Power Consumption
The CS5531/32/33/34 accommodate three power
consumption modes: normal, standby, and sleep.
The default mode, “normal mode”, is entered after
power is applied. In this mode, the
CS5531/32/33/34-AS versions typically consume
35 mW. The CS5532/34-BS versions typically
consume 70 mW. The other two modes are referred
to as the power save modes. They power down
most of the analog portion of the chip and stop filter
convolutions. The power save modes are entered
whenever the power down (PDW) bit of the config-
uration register is set to logic 1. The particular pow-
er save mode entered depends on state of the PSS
(Power Save Select) bit. If PSS is logic 0, the con-
verter enters the standby mode reducing the power
consumption to 4 mW. The standby mode leaves
the oscillator and the on-chip bias generator for the
analog portion of the chip active. This allows the
converter to quickly return to the normal mode
once PDW is set back to a logic 1. If PSS and PDW
are both set to logic 1, the sleep mode is entered re-
ducing the consumed power to around 500 µW.
Since this sleep mode disables the oscillator, ap-
proximately a 20 ms oscillator start-up delay period
is required before returning to the normal mode. If
an external clock is used, there will be no delay.
Further note that when the chips are used in the
Gain = 1 mode, the PGIA is powered down. With
the PGIA powered down, the power consumed in
the normal power mode is reduced by approximate-
ly 1/2. Power consumption in the sleep and standby
modes is not affected by the amplifier setting.
2.3.2. System Reset Sequence
The reset system (RS) bit permits the user to per-
form a system reset. A system reset can be initiated
at any time by writing a logic 1 to the RS bit in the
configuration register. After the RS bit has been
set, the internal logic of the chip will be initialized
to a reset state. The reset valid (RV) bit is set indi-
cating that the internal logic was properly reset.
DS289PP5
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