CS5534-AS View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CS5534-AS' PDF : 52 Pages View PDF
CS5531/32/33/34
initialized, all the Setups point to their default
settings irrespective of the conversion or
calibration mode (i.e conversions can be
performed, but only physical channel 1 will be
converted). Further note that filter
convolutions are reset (i.e. flushed) if
consecutive conversions are performed on
two different physical channels. If
consecutive conversions are performed on
the same physical channel, the filter is not
reset. This allows the ADCs to more quickly
settle full scale step inputs.
2.7. Using Multiple ADCs Synchronously
Some applications require synchronous data out-
puts from multiple ADCs converting different ana-
log channels. Multiple CS5531/32/33/34 parts can
be synchronized in a single system by using the fol-
lowing guidelines:
1) All of the ADCs in the system must be operated
from the same oscillator source.
2) All of the ADCs in the system must share com-
mon SCLK and SDI lines.
3) A software reset must be performed at the same
time for all of the ADCs after system power-up (by
selecting all of the ADCs using their respective CS
pins, and writing the reset sequence to all parts, us-
ing SDI and SCLK).
4) A start conversion command must be sent to all
of the ADCs in the system at the same time. The ±
8 clock cycles of ambiguity for the first conversion
(or for a single conversion) will be the same for all
ADCs, provided that they were all reset at the same
time.
5) Conversions can be obtained by monitoring
SDO on only one ADC, (bring CS high for all but
one part) and reading the data out of each part indi-
vidually, before the next conversion data words are
ready.
An example of a synchronous system using two
CS5532 parts is shown in Figure 15.
CS5532
SDO
SDI
SCLK
CS
OSC2
µC
CS5532
SDO
SDI
SCLK
CS
OSC2
CLOCK
SOURCE
Figure 15. Synchronizing Multiple ADCs
2.8. Conversion Output Coding
The CS5531/32/33/34 output 16-bit (CS5531/33)
and 24-bit (CS5532/34) data conversion words. To
read a conversion word the user must read the con-
version data register. The conversion data register
is 32 bits long and outputs the conversions MSB
first. The last byte of the conversion data register
contains data monitoring flags. The channel indica-
tor (CI) bits keep track of which physical channel
was converted and the overrange flag (OF) moni-
tors to determine if a valid conversion was per-
formed. Refer to the Conversion Data Output
Descriptions section for more details.
The CS5531/32/33/34 output data conversions in
binary format when operating in unipolar mode and
in two's complement when operating in bipolar
mode. Tables 4 and 5 show the code mapping for
both unipolar and bipolar mode. VFS in the tables
refers to the positive full-scale voltage range of the
converter in the specified gain range, and -VFS re-
fers to the negative full-scale voltage range of the
converter. The total differential input range (be-
tween AIN+ and AIN-) is from 0 to VFS in unipo-
lar mode, and from -VFS to VFS in bipolar mode.
38
DS289PP5
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