CS61535A-IL1 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CS61535A-IL1' PDF : 48 Pages View PDF
CS61535A
The receiver uses an edge detector and a continu-
ously calibrated delay line to generate the
recovered clock. The delay line divides its refer-
ence clock, ACLKI or the jitter attenuator’s
oscillator, into 13 equal divisions or phases. Con-
tinuous calibration assures timing accuracy, even
if temperature or power supply voltage fluctuate.
The leading edge of an incoming data pulse trig-
gers the clock phase selector. The phase selector
chooses one of the 13 available phases which the
delay line produces for each bit period. The out-
put from the phase selector feeds the clock and
data recovery circuits which generate the recov-
ered clock and sample the incoming signal at
appropriate intervals to recover the data. The jitter
tolerance of the receiver exceeds that shown in
Figure 12.
300
100
28
PEAK
TO
10
PEAK
JITTER
(unit intervals)
1
.4
.1
0
10
100 300 700 1k
10k
100k
JITTER FREQUENCY (Hz)
Figure 12. Input Jitter Tolerance of Receiver
The CS61535A outputs a clock immediately upon
power-up. The clock recovery circuit is cali-
brated, and the device will lock onto the AMI
data input immediately. If loss of signal occurs,
the RCLK frequency will equal the ACLKI fre-
quency.
In the Hardware Mode, data at RPOS and RNEG
is stable and may be sampled on the rising edge
of the recovered clock. In the Extended Hardware
Mode, data at RDATA is stable and may be sam-
pled on the falling edge of the recovered clock. In
DS40F2
the Host Mode, CLKE determines the clock po-
larity for which output data is stable and valid as
shown in Table 5.
MODE
(pin 5)
LOW
(<0.2V)
HIGH
(>(V+) - 0.2V)
CLKE
(pin 28)
X
LOW
HIGH
(>(V+) - 0.2V)
HIGH
MIDDLE
X
(2.5V)
X = Don’t care
DATA
RPOS
RNEG
RPOS
RNEG
SDO
RPOS
RNEG
SDO
RDATA
CLOCK Clock Edge for
Valid Data
RCLK
RCLK
Rising
Rising
RCLK
RCLK
SCLK
Rising
Rising
Falling
RCLK
RCLK
SCLK
Falling
Falling
Rising
RCLK
Falling
Table 5. Data Output/Clock Relationship
Jitter and Recovered Clock
The CS61535A are designed for error free clock
and data recovery from an AMI encoded data
stream in the presence of more than 0.4 unit inter-
vals of jitter at high frequency. The clock
recovery circuit is also tolerant of long strings of
zeros. The edge of an incoming data bit causes
the circuitry to choose a phase from the delay line
which most closely corresponds with the arrival
time of the data edge, and that clock phase trig-
gers a pulse which is typically 140 ns in duration.
This phase of the delay line will continue to be
selected until a data bit arrives which is closer to
another of the 13 phases, causing a new phase to
be selected. The largest jump allowed along the
delay line is six phases.
When an input signal is jitter free, the phase se-
lection will occasionally jump between two
adjacent phases resulting in RCLK jitter with an
amplitude of 1/13 UIpp. These single phase
jumps are due to differences in frequency of the
incoming data and the calibration clock input to
ACLKI. For T1 operation of the CS61535A, the
instantaneous period can be 14/13 * 648 ns = 698
ns (1,662,769 Hz) or 12/13 * 648 ns = 598 ns
(1,425,231 Hz) when adjacent clock phases are
chosen. As long as the same phase is chosen, the
15
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