CS61884 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CS61884' PDF : 72 Pages View PDF
CS61884
14. REGISTER DESCRIPTIONS
14.1 Revision/IDcode Register (00h)
BIT NAME
Description
[7:4] REVI 7-4 Bits [7:4] are taken from the least-significant nibble of the Device IDCode, which are 0100.
(Refer to Device ID Register (IDR) (See Section 16.3 on page 48).
Bits [3:0] are the revision bits from the JTAG IDCODE register, CS61884 Revision A = 0000.
[3:0] REVI 3-0 These bits are subject to change with the revision of the device (Refer to Device ID Register
(IDR) (See Section 16.3 on page 48).
14.2 Analog Loopback Register (01h)
BIT NAME
Description
Enables analog loopbacks. A “1” in bit n enables the loopback for channel n. Refer to Analog
[7:0] ALBK 7-0 Loopback (See Section 12.2 on page 29) for a complete explanation. Register bits default
to 00h after power-up or reset.
14.3 Remote Loopback Register (02h)
BIT NAME
Description
Enables remote loopbacks. A “1” in bit n enables the loopback for channel n. Refer to
[7:0] RLBK 7-0 Remote Loopback (See Section 12.4 on page 30) for a complete explanation. Register bits
default to 00h after power-up or reset.
14.4 TAOS Enable Register (03h)
BIT NAME
Description
[7:0] TAOE 7-0 A “1” in bit n of this register turns on the TAOS generator in channel n. Register bits default
to 00h after power-up or reset.
14.5 LOS Status Register (04h)
BIT NAME
Description
[7:0] LOSS 7-0 Register bit n is read as “1” when LOS is detected on channel n. Register bits default to
00h after power-up or reset.
14.6 DFM Status Register (05h)
BIT NAME
Description
[7:0] DFMS 7-0 Driver Failure Monitor. The DFM will set bit n to “1” when it detects a short circuit in channel
n. Register bits default to 00h after power-up or reset.
DS485PP4
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