82C55A
Timing Waveforms (Continued)
A0-A1,
CS
DATA
BUS
WR
tAW (7)
tWA (8)
tDW (10) tWD (11)
tWW (9)
FIGURE 30. WRITE TIMING
AC Test Circuit
OUTPUT FROM
DEVICE UNDER
TEST
V1
R1
R2
TEST
POINT
C1
(SEE NOTE)
NOTE: Includes STRAY and JIG Capacitance
A0-A1,
CS
RD
DATA
BUS
tAR (1)
tRR (3)
(4) tRD
VALID
HIGH IMPEDANCE
FIGURE 31. READ TIMING
tRA (2)
tDF (5)
AC Testing Input, Output Waveforms
INPUT
VIH + 0.4V
1.5V
1.5V
OUTPUT
VOH
VIL - 0.4V
VOL
AC Testing: All AC Parameters tested as per test circuits. Input RISE
and FALL times are driven at 1ns/V.
TEST CONDITION DEFINITION TABLE
TEST CONDITION
V1
R1
R2
1
1.7V
523 Open
2
VCC
2k
1.7k
3
1.5V
750 Open
C1
150pF
50pF
50pF
FN2969 Rev 11.00
Dec 8, 2015
Page 22 of 30