CS8421-CNZ View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CS8421-CNZ' PDF : 36 Pages View PDF
CS8421
Parameters
Master Mode (Note 9)
I/OSCLK Frequency (non-TDM)
OSCLK Frequency (TDM)
I/OLRCK Duty Cycle
I/OSCLK Duty Cycle
I/OSCLK Falling Edge to I/OLRCK Edge
OSCLK Falling Edge to OLRCK Edge (TDM)
OSCLK Falling Edge to SDOUT Output Valid
SDIN/TDM_IN Setup Time Before I/OSCLK Rising Edge
SDIN/TDM_IN Hold Time After I/OSCLK Rising Edge
I/OLRCK
(input)
I/OSCLK
(input)
SDIN
(input)
SDOUT
(output)
tlckd
tlcks
tsckh
tsckl
tds
tdh
MSB
tdpd
MSB
MSB-1
MSB-1
Figure 1. Non-TDM Slave Mode Timing
Symbol Min
Max Units
tlcks
tfss
tdpd
tds
tdh
tlrckh
64*Fsi/o
256*Fso
45
55
45
55
-
5
-
5
-
7
3
-
5
-
MHz
MHz
%
%
ns
ns
ns
ns
ns
OLRCK
(input)
tfss
tfsh
tsckh
tsckl
OSCLK
(input)
TDM_IN
(input)
SDOUT
(output)
tds
tdh
MSB
tdpd
MSB
Figure 2. TDM Slave Mode Timing
MSB-1
MSB-1
6. After powering up the CS8421, RST should be held low until the power supplies and clocks are settled.
7. The maximum possible sample rate is XTI/128.
8. OLRCK must remain high for at least 8 OSCLK periods in TDM Mode.
9. Only the input or the output serial port can be set as master at a given time.
I/OLRCK
(output)
tlcks
OLRCK
(output)
I/OSCLK
(output)
tds
tdh
OSCLK
(output)
SDIN
(input)
tdpd
SDOUT
(output)
MSB
MSB
MSB-1
TDM_IN
(input)
MSB-1
SDOUT
(output)
Figure 3. Non-TDM Master Mode Timing
tfss
tds
tdh
MSB
tdpd
MSB
Figure 4. TDM Master Mode Timing
MSB-1
MSB-1
14
DS641F4
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