CS8900-CQ3 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CS8900-CQ3' PDF : 138 Pages View PDF
CS8900A
Crystal LAN™ ISA Ethernet Controller
Register 3, RxCFG
Bit
Bit Name
Operation
7
StreamE When set, Stream Transfer
enabled.
9
RxDMAonly When set, DMA slave opera-
tion used for all receive
frames.
A AutoRX DMAE When set, Auto-Switch DMA
enabled.
B
BufferCRC When set, the received CRC
is buffered.
Register 17, BusCTL
Bit
Bit Name
Operation
B
DMABurst When set, DMA operations
hold the bus for up to approx-
imately 28 µs. When clear,
DMA operations are continu-
ous.
D
RxDMAsize When set, DMA buffer size is
64 Kbytes. When clear, DMA
buffer size is 16 Kbytes.
Table 22. Receive Frame Pre-Processing
5.2.3 Receive Frame Pre-Processing
The CS8900A pre-processes all receive frames us-
ing a four step process:
1) Destination Address filtering;
2) Early Interrupt Generation;
3) Acceptance filtering; and,
4) Normal Interrupt Generation.
Figure 21 provides a diagram of frame pre-process-
ing.
5.2.3.1 Destination Address Filtering
All incoming frames are passed through the Desti-
nation Address filter (DA filter). If the frame’s DA
passes the DA filter, the frame is passed on for fur-
ther pre-processing. If it fails the DA filter, the
frame is discarded. See Section 5.3 on page 86 for
a more detailed description of DA filtering.
Receive Frame
Destination
Address Filter
Check:
- PromiscuousA?
- IAHashA?
- MulticastA?
- IndividualA?
- BroadcastA?
Pass No
DA Filter?
Discard Frame
Yes
Generate Early
Interrupts if Enabled
(see next figure)
Acceptance Filter
Check:
- RxOKA?
- ExtradataA?
- RuntA?
- CRCerrorA?
Yes
Status of receive
frame reported in
RxEvent register,
frame accepted
into on-chip RAM
Pass
Accept.
Filter?
No
Status of receive
frame reported in
RxEvent register,
frame discarded.
Generate Interrupts
Check:
- RxOKiE?
- ExtradataiE?
- CRCerroriE?
- RuntiE?
- RxDMAiE?
Pre-Processing
Complete
Figure 21. Receive Frame Pre-Processing
CIRRUS LOGIC PRODUCT DATASHEET
82
DS271PP4
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