CS8900-IQ3 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CS8900-IQ3' PDF : 138 Pages View PDF
CS8900A
Crystal LAN™ ISA Ethernet Controller
Suffix
CMD
CFG
CTL
Event
ST
Type
Read/Write
Read/Write
Read/Write
Read-only
Read-only
Read-only
Description
Command: Written once per frame to initiate transmit.
Configuration: Written at setup and used to determine
what frames will be transmitted and received and what
events will cause interrupts.
Control: Written at setup and used to determine what
frames will be transmitted and received and how the physi-
cal interface will be configured.
Event: Reports the status of transmitted and received
frames.
Status: Reports information about the configuration of the
CS8900A.
Counters: Counts missed receive frames and collisions.
Provides time domain for locating coax cable faults.
Comments
cleared when read
cleared when read
Table 13. PacketPage Register Types
Section 4.4.4 on page 48 provides a detailed de- (Register B). Each Interrupt Enable bit corresponds
scription of the bits in each register.
to a specific event. If an Interrupt Enable bit is set
4.4.3.1 Act-Once Bits
There are four bits that cause the CS8900A to take
a certain action only once when set. These "Act-
Once" bits are: Skip_1 (Register 3, RxCFG, Bit 6),
RESET (Register 15, SelfCTL, Bit 6), ResetRxD-
MA (Register 17, BusCTL, Bit 6), and SWint-X
(Register B, BufCFG, Bit 6). To cause the action
again, the host must set the bit again. Act-Once bits
are always read as clear.
and its corresponding event occurs, the CS8900A
generates an interrupt to the host processor.
The bits that report when various events occur are
located in three Event registers and two counters.
The Event registers are RxEvent (Register 4), Tx-
Event (Register 8), and BufEvent (Register C). The
counters are RxMISS (Register 10) and TxCOL
(Register 12). Each Interrupt Enable bit and its as-
sociated Event are identified in Table 14.
4.4.3.2 Temporal Bits
Temporal bits are bits that are set and cleared by the
CS8900A without intervention of the host proces-
sor. This includes all status bits in the three status
registers (Register 14, LineST; Register 16,
An Event bit will be set whenever the specified
event happens, whether or not the associated Inter-
rupt Enable bit is set. All Event registers are cleared
upon read-out by the host.
4.4.3.4 Accept Bits
SelfST; and, Register 18, BusST), the RxDest bit There are nine Accept bits located in the RxCTL
(Register C, BufEvent, Bit F), and the Rx128 bit register (Register 5), each of which is followed by
(Register C, BufEvent, Bit B). Like all Event bits, the suffix A. Accept bits indicate which types of
RxDest and Rx128 are cleared when read by the frames will be accepted by the CS8900A. (A frame
host.
is said to be "accepted" by the CS8900A when the
4.4.3.3 Interrupt Enable Bits and Events
Interrupt Enable bits end with the suffix iE and are
located in three Configuration registers: RxCFG
(Register 3), TxCFG (Register 7), and BufCFG
frame data are placed in either on-chip memory, or
in host memory by DMA.) Four of these bits have
corresponding Interrupt Enable (iE) bits. An Ac-
cept bit and an Interrupt Enable bit are independent
CIRRUS LOGIC PRODUCT DATASHEET
DS271PP4
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