CS8900A-IQ3Z View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CS8900A-IQ3Z' PDF : 138 Pages View PDF
CS8900A
Crystal LAN™ Ethernet Controller
• updates the DMA Start-of-Frame register
(PacketPage base + 0026h);
• updates the DMA Frame Count register
(PacketPage base + 0028h);
• updates DMA Byte Count register (Pack-
etPage base + 002Ah);
• sets the RxDMAFrame bit (Register C,
BufEvent, Bit 7); and,
• generates an RxDMAFrame interrupt.
5.5.4 Keeping StreamTransfer Mode
Active
When the CS8900A initiates a StreamTransfer
cycle, it will continue to execute cycles as long
as the following conditions hold true:
• all packets received are of legal length with
valid CRC;
• each packet follows its predecessor by less
than 52 ms; and,
• the DA of each packet passes the DA filter.
If any of these conditions are not met, the
CS8900A exits StreamTransfer by generating
RxOK and RxDMA interrupts. The CS8900A
then returns to either Memory, I/O, or DMA
mode, depending on configuration.
5.5.5 Example of StreamTransfer
Figure 28 shows how four back-to-back
frames, followed by five back-to-back frames,
would be received without StreamTransfer.
Figure 29 shows how the same sequence of
frames would be received with StreamTrans-
fer.
4 Back-to-Back Fram es
T > 52 us
5 Back-to-Back Fram es
Interrupt
Request
9 Interrupts for 9 "Good" Packets
Time
Figure 28. Receive Example Without Stream Transfer
4 Back-to-Back Fram es
T > 52 us
5 Back-to-Back Fram es
Interrupt
Request
2 Interrupts for 9 "Good" Packets
Time
Figure 29. Receive DMA Configuration Options
CIRRUS LOGIC PRODUCT DATASHEET
98
DS271F4
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