CS8920A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CS8920A' PDF : 144 Pages View PDF
CS8920A
Test Mode
AUI Internal
Loopback
AUI External
Loopback
AUI Collision
AUIloop
1
1
0
ENDECloop
Description of Test
1
Transmit a frame and verify that the frame is received without error.
0
Connect DO+ to DI+ and D0- to DI-. Transmit a frame and verify
that the frame is received without error (since there is no collision
signal, an SQE error will occur).
0
Start transmission and observe DO+/DO- activity. Input a 10 MHz
sine wave to CI+/CI- pins and observe collisions.
Table 6.2. AUI Loopback and Collision Tests
6.1 Boundary Scan
Boundary Scan test mode provides an easy and
efficient board-level test for verifying that the
CS8920A has been installed properly. Boundary
Scan will check to see if the orientation of the
chip is correct, and if there are any open or short
circuits.
Boundary Scan is controlled by the TEST pin.
When TEST is high, the CS8920A is configured
for normal operation. When TEST is low, the
following occurs:
• the CS8920A enters Boundary Scan test
mode and stays in this mode as long as
TEST is low;
• the CS8920A goes through an internal reset
and remains in internal reset as long as
TEST is low;
• the AEN pin, normally the ISA bus Address
Enable, is redefined to become the Boundary
Scan shift clock input; and
• all digital outputs and bi-directional pins are
placed in a high-impedance state (this electri-
cally isolates the CS8920A digital outputs
from the rest of the circuit board).
For Boundary Scan to be enabled, AEN must be
low before TEST is driven low.
DS238PP2
A complete Boundary Scan test is made up of
two separate cycles. The first cycle, known as the
Output Cycle, tests all digital output pins and all
bi-directional pins. The second cycle, known as
the Input Cycle, tests all digital input pins and all
bi-directional pins.
Output Cycle
During the Output Cycle, the falling edge of
AEN causes each of the 26 digital output pins
and each of the 16 bi-directional pins to be
driven low, one at a time. The cycle begins with
LINKLED and advances in order counterclock-
wise around the chip though all 42 pins. This test
is referred to as a "walking 0" test.
The following is a list of output pins and bi-di-
rectional pins that are tested during the Output
Cycle:
Pin Name
EECS
EESK
LOCALLED
EEDO
DRQ7
DRQ6
DRQ5
CSOUT
SD08-SD15
IRQ15
IRQ14
IRQ12
IRQ11
IRQ10
Pin #
141
142
5
6
9
14
16
8
27-24,21-18
31
30
32
33
34
Pin Name
IRQ2/9
IRQ7
IRQ6
IRQ5
IRQ4
IRQ3
IOCS16
MCS16
IOCHRDY
SD0 - SD7
BSTATUS
LINKLED
LANLED
EWAKE
Pin #
106
79
78
77
76
75
43
44
92
96-99,102-105
113
139
140
3
121
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