CS8920A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CS8920A' PDF : 144 Pages View PDF
4.5 Status and Control Register Detailed
Description
CS8920A
Register 0: Interrupt Status Queue (ISQ, Read-only)
Address: PacketPage base + 0120h
F-6
RegContent
5-0
RegNum
The Interrupt Status Queue Register is used in both Memory Mode and I/O Mode to provide the host with
interrupt information. Whenever an event occurs that triggers an enabled interrupt, the CS8920A sets the appro-
priate bit(s) in one of five registers, maps the contents of that register to the ISQ register, and drives an IRQ pin
high. Three of the registers mapped to ISQ are event registers: RxEvent (Register 4), TxEvent (Register 8), and
BusEvent (Register C). The other two registers are counter-overflow reports: RxMISS (Register 10) and TxCOL
(Register 12). In Memory Mode, ISQ is located at PacketPage base + 120h. In I/O Mode, ISQ is located at I/O
Base + 0008h. See Section 5.1. A read of ISQ 0000 indicates that there are no pending interrupts.
BIT NAME
DESCRIPTION
5-0 RegNum
The lower six bits describe which register (4, 8, C, 10 or 12) is contained in the ISQ.
6
RegContent The upper ten bits contain the register data contents.
This register’s initial state after reset is: 0000 0000 0000 0000
50
DS238PP2
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