CS8920A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CS8920A' PDF : 144 Pages View PDF
CS8920A
Register D: Advance Interrupt Control and Status
(ADVintCTL/ST, Read/Write)
Address: PacketPage base + 010Ch
F
E
D
C
B
A
9
8
7
6
5-0
Timer
Enable
Mode
Rx48/64iE Rx64
Rx48/64 Timer irq 001101
irq
This register contains control bits for various interrupt sources and the status bits of those sources.
BIT NAME
DESCRIPTION
5-0 001101
These bits provide an internal address used by the CS8920A to identify this as the
Buffer Configuration Register.
6
Timer irq
When set, a timer-based interrupt has occurred (when IDT exceeds the PDV). This can
happen only when bit F (Timer Enable) is set.
7
Rx48/64 irq When set, an interrupt based on 48/64 bytes of received data has occurred. The status
bit is read only; it is reset when the bit is read.
A
Rx64
This is a 64-byte interrupt. It is only applicable when Rx48/64iE is set.
B
Rx48/64iE
Interrupt enabled. If set to one, a 48- or 64-byte interrupt will be generated. The type of
interrupt depends on bit A, the Rx64 control bit. If cleared to 0, no interrupt will be
generated.
E
Mode
Used only for the IDT/PDV timer mechanism. This determines how often an interrupt
will automatically get generated. If the Timer-generated interrupt is to be used, (Timer
Enable bit is set) then the Mode bit takes on this meaning:
Mode = 0 The Programmable Delay Value (PDV) register is reset to FFFFh following
the interrupt generation and must be reprogrammed by the host. This will prevent
generation of a second interrupt. The Interrupt Delay Timer (IDT) is restarted only on a
read of the Byte Counter. If the Byte Counter is never read, a second interrupt will not
be generated.
Mode = 1 The IDT will be restarted on a read of the Byte Counter or when an interrupt
event is seen. This mode allows a periodic interrupt because the exiting of an interrupt
sequence/routine is accomplished by reading the ISQ. This will start the timer again.
The PDV remains at its programmed value.
F
Timer Enable Must be set to 1 to allow a timer-driven interrupt to occur. This enables the interrupt
being generated from the PDV and IDT.
This register’s initial state after reset is: 0000 0000 0000 1101
60
DS238PP2
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