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CS98100-CM View Datasheet(PDF) - Cirrus Logic

Part Name
Description
MFG CO.
CS98100-CM
Cirrus-Logic
Cirrus Logic Cirrus-Logic
'CS98100-CM' PDF : 60 Pages View PDF
CS98100
1.2.5 Digital Audio Interface Timing
Figure 8 and Figure 9 illustrate the signal timing for the digital audio pins. The bi-directional AUD_XCK
pin clocks at 8x the frequency of the AUD_BCK pin. The AUD_BCK pin outputs at 32x or 48x of the
sample frequency, and transitions on the falling edge of the AUD_XCK pin. AUD_BCK is shown without
polarity to indicate the polarity is programmable.
Symbol
tslri
tsdi
thsdi
Description
AIN_LRCK setup to AUD_BCK active edge
Min
25
AIN_DATA setup to AUD_BCK active edge
25
AIN_DATA hold time after AUD_BCK active edge 1
Typ Max Unit
-
ns
-
ns
-
ns
Table 5. Digital Audio In Characteristics
*AUD_BCK (Output)
AIN_LRCK (Input)
t lrts
tsdsus tsdhs
AIN_DATA (Input)
* Active clock edge is programmable. Timing is referenced from active edge.
Figure 8. Digital Audio In Timing Diagram
13
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