CSB480E View Datasheet(PDF) - Hynix Semiconductor
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Description
MFG CO.
'CSB480E' PDF : 106 Pages View PDF
Chapter 2. Architecture
State Counter (SC)
A fundamental machine cycle timing chart is shown below. Every instruction is
one byte length. Its execution time is the same. Execution of one instruction
takes 6 clocks for fetch cycle and 6 clocks for execute cycle (12 clocks in total).
Virtually these two cycles proceed simultaneously, and thus it is apparently
completed in 6 clocks (one machine cycle). Exceptionally BR, CAL and RTN
instructions is normal execution time since they change an addressing
sequencially. Therefore, the next instruction is prefetched so that its execution
is completed within the fetch cycle.
T1 T2 T3 T4 T5 T6 T1 T2 T3 T4 T5 T6
Fetch cycle N
Execute cycle N-1
Execute cycle N
Fetch cycle N-1
Phase¥°
Phase¥±
Phase¥²
Machine
Cycle
Machine
Cycle
Fig. 2-3 Fundamental timing chart
2- 5
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