CXP973F064 View Datasheet(PDF) - Sony Semiconductor
Part Name
Description
MFG CO.
'CXP973F064' PDF : 42 Pages View PDF
CXP973F064
(6) I2C bus
(Topr = –30 to +85°C, VDD = 2.7 to 3.6V, Vss = 0V reference)
Item
Symbol Pins
SCK clock frequency
tSCL
Bus free time between stop
and start conditions
tBUF
SCL
SDA
Hold time under (resend)
start condition
tHD;STA
Hold time in SCL clock low
state
tLow
SDA,
SCL
SCL
Hold time in SCL clock high
state
tHigh
SCL
Setup time under (resend)
start condition
tSU;STA
SDA,
SCL
Data hold time
tHD;DAT
SDA,
SCL
Data setup time
SCL, SDA signal output
rise time
SCL, SDA signal output
fall time
Setup time under stop
condition
tSU;DAT
tRd,
tRc
tFd,
tFc
tSU;STO
SDA,
SCL
SDA,
SCL
SDA,
SCL
SDA,
SCL
∗1 Due to the total capacitance of the bus.
Standard mode
Min.
Max.
100
4.7
4.0
4.7
4.0
4.7
0
250
1000
300
4.0
High-speed mode
Unit
Min.
Max.
400 kHz
1.3
µs
0.6
µs
1.3
µs
0.6
µs
0.6
µs
0
0.9
µs
100
ns
20 + α∗1
300
ns
20 + α∗1
300
ns
0.6
µs
tBUF
SDA
tRd
tFd
tSCL
tRc
tLow
tSU;DAT
tFc
SCL
tHD;STA
tHD;DAT
tHigh
Fig. 8. I2C bus timing
– 29 –
tHD;STA
tSU;STA
tSU;STO
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