CY7B993V-5AXC View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
MFG CO.
'CY7B993V-5AXC' PDF : 15 Pages View PDF
RoboClock
CY7B993V
CY7B994V
Table 1. Frequency Range Select
Table 3. Output Skew Select Function
FS[2]
LOW
MID
HIGH
CY7B993V
fNOM (MHz)
Min.
Max.
12
26
24
52
48
100
CY7B994V
fNOM (MHz)
Min.
Max.
24
52
48
100
96
200
Time Unit Definition
Selectable skew is in discrete increments of time unit (tU). The
value of a tU is determined by the FS setting and the maximum
nominal output frequency. The equation to be used to
determine the tU value is as follows:
tU = 1/(fNOM*N).
N is a multiplication factor which is determined by the FS
setting. fNOM is nominal frequency of the device. N is defined
in Table 2.
Table 2. N Factor Determination
Function
Selects
Output Skew Function
[1:4]F0
Feed-
and
back
[1:4]F1 FBF0 Bank1 Bank2 Bank3 Bank4 Bank
LOW
LOW
LOW
MID
MID
MID
HIGH
HIGH
HIGH
LOW
MID
HIGH
LOW
MID
HIGH
LOW
MID
HIGH
–4tU
–3tU
–2tU
–1tU
0tU
+1tU
+2tU
+3tU
+4tU
–4tU
–3tu
–2tU
–1tU
0tU
+1tU
+2tU
+3tU
+4tU
–8tU
–7tU
–6tU
BK1[3]
–8tU
–7tU
–6tU
BK1[3]
0tU
0tU
BK2[3] BK2[3]
+6tU
+7tU
+8tU
+6tU
+7tU
+8tU
–4tU
NA
NA
NA
0tu
NA
NA
NA
+4tU
FS
LOW
MID
HIGH
CY7B993V
CY7B994V
fNOM (MHz) at
fNOM (MHz) at
N which tU =1.0 ns N which tU =1.0 ns
64
15.625
32
31.25
32
31.25
16
62.5
16
62.5
8
125
Divide and Phase Select Matrix
The Divide and Phase Select Matrix is comprised of five
independent banks: four banks of clock outputs and one bank
for feedback. Each clock output bank has two pairs of
low-skew, high-fanout output buffers ([1:4]Q[A:B][0:1]), two
phase function select inputs ([1:4]F[0:1]), two divider function
selects ([1:4]DS[0:1]), and one output disable (DIS[1:4]).
Table 4. Output Divider Function
Function
Selects
Output Divider Function
[1:4]DS1 [1:4]DS0
Feed-
and
and Bank Bank Bank Bank back
FBDS1 FBDS0
1
2
3
4
Bank
LOW LOW /1
/1
/1
/1
/1
LOW MID
/2
/2
/2
/2
/2
LOW HIGH /3
/3
/3
/3
/3
MID LOW /4
/4
/4
/4
/4
MID
MID
/5
/5
/5
/5
/5
The feedback bank has one pair of low-skew, high-fanout
output buffers (QFA[0:1]). One of these outputs may connect
to the selected feedback input (FBK[A:B]±). This feedback
bank also has one phase function select input (FBF0), two
divider function selects FSDS[0:1], and one output disable
(FBDIS).
MID HIGH /6
/6
/6
/6
/6
HIGH LOW /8
/8
/8
/8
/8
HIGH MID /10 /10 /10 /10 /10
HIGH HIGH /12 /12 /12 /12 /12
The phase capabilities that are chosen by the phase function
select pins are shown in Table 3. The divide capabilities for
each bank are shown in Table 4.
Figure 1 illustrates the timing relationship of programmable
skew outputs. All times are measured with respect to REF with
the output used for feedback programmed with 0tU skew. The
PLL naturally aligns the rising edge of the FB input and REF
input. If the output used for feedback is programmed to
another skew position, then the whole tU matrix will shift with
respect to REF. For example, if the output used for feedback
is programmed to shift –8tU, then the whole matrix is shifted
forward in time by 8tU. Thus an output programmed with 8tU
of skew will effectively be skewed 16tU with respect to REF.
Notes:
2. The level to be set on FS is determined by the “nominal” operating frequency (fNOM) of the VCO and Phase Generator. fNOM always appears on an output when
the output is operating in the undivided mode. The REF and FB are at fNOM when the output connected to FB is undivided.
3. BK1, BK2 denotes following the skew setting of Bank1 and Bank2, respectively.
Document #: 38-07127 Rev. *F
Page 5 of 15
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