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CY7B994V-5AXC View Datasheet(PDF) - Cypress Semiconductor

Part Name
Description
MFG CO.
CY7B994V-5AXC
Cypress
Cypress Semiconductor Cypress
'CY7B994V-5AXC' PDF : 15 Pages View PDF
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RoboClock
CY7B993V
CY7B994V
Switching Characteristics Over the Operating Range[9, 10, 11, 12, 13] (continued)
CY7B993/4V-2
CY7B993/4V-5
Parameter
Description
Min. Typ. Max. Min. Typ. Max. Unit
TTB
Total Timing Budget window (same frequency and phase)[17,
– 500 –
– 700 ps
18]
tPDDELTA
tREFpwh
tREFpwl
tr/tf
Propagation Delay difference between two devices[17]
REF input (Pulse Width HIGH)[19]
REF input (Pulse Width LOW)[19]
Output Rise/Fall Time[20]
– – 200 –
– 200 ps
2.0 –
– 2.0 –
ns
2.0 –
– 2.0 –
ns
0.15 – 2.0 0.15 – 2.0 ns
tLOCK
PLL Lock Time From Power-up
– – 10 –
– 10 ms
tRELOCK1 PLL Relock Time (from same frequency, different phase)
with Stable Power Supply
500 –
500 µs
tRELOCK2
tODCV
tPWH
tPWL
tPDEV
PLL Relock Time (from different frequency, different phase)
with Stable Power Supply[21]
Output duty cycle deviation from 50%[13]
Output HIGH time deviation from 50%[22]
Output LOW time deviation from 50%[22]
–1.0
Period deviation when changing from reference to
reference[23]
1000 –
1.0 –1.0
1.5 –
2.0 –
0.025 –
1000 µs
1.0 ns
1.5 ns
2.0 ns
0.025 UI
tOAZ
DIS[1:4]/FBDIS HIGH to output high-impedance from
ACTIVE[14, 24]
1.0
10 1.0
10
ns
tOAZ
DIS[1:4]/FBDIS LOW to output ACTIVE from output
high-impedance[24, 25]
0.5
14 0.5
14
ns
AC Test Loads and Waveform[26]
3.3V
R1
For LOCK output only For all other outputs
OUTPUT
R1 = 910
R2 = 910
R1 = 100
R2 = 100
CL
CL < 30 pF
CL < 25 pF to 185 MHz
R2
(Includes fixture and or 10 pF at 200 MHz
probe capacitance)
(a) LVTTL AC Test Load
3.3V
GND
< 1 ns
2.0V
0.8V
2.0V
0.8V
< 1 ns
(b) TTL Input Test Waveform
Notes:
18. TTB is the window between the earliest and the latest output clocks with respect to the input reference clock across variations in output frequency, supply voltage,
operating temperature, input clock edge rate, and process. The measurements are taken with the AC test load specified and include output-output skew, cycle-cycle
jitter, and dynamic phase error. TTB will be equal to or smaller than the maximum specified value at a given frequency.
19. Tested initially and after any design or process changes that may affect these parameters.
20. Rise and fall times are measured between 2.0V and 0.8V.
21. fNOM must be within the frequency range defined by the same FS state.
22. tPWH is measured at 2.0V. tPWL is measured at 0.8V.
23. UI = Unit Interval. Examples: 1 UI is a full period. 0.1UI is 10% of period.
24. Measured at 0.5V deviation from starting voltage.
25. For tOZA minimum, CL = 0 pF. For tOZA maximum, CL= 25 pF to 185 MHz or 10 pF to 200 MHz.
26. These figures are for illustrations only. The actual ATE loads may vary.
Document #: 38-07127 Rev. *F
Page 10 of 15
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