CY7C037AV-20AXC View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
MFG CO.
'CY7C037AV-20AXC' PDF : 24 Pages View PDF
CY7C027V/027VN/027AV/028V
CY7C037V/037AV/038V
Switching Waveforms(continued)
A0–A 2
SEM
Figure 9. Semaphore Read After Write Timing, Either Side[29]
VALID ADRESS
tSAA
VALID ADRESS
tAW
tHA
tSCE
tSOP
tACE
tOHA
I/O 0
R/W
OE
tSD
DATAIN VALID
tSA
tPWE
tHD
DATAOUT VALID
WRITE CYCLE
tSWRD
tSOP
tDOE
READ CYCLE
A0L –A2L
R/WL
SEM L
A 0R–A2R
R/WR
SEM R
Figure 10. Timing Diagram of Semaphore Contention[30, 31, 32]
MATCH
tSPS
MATCH
Notes
29. CE = HIGH for the duration of the above timing (both write and read cycle).
30. I/O0R = I/O0L = LOW (request semaphore); CER = CEL = HIGH.
31. Semaphores are reset (available to both ports) at cycle start.
32. If tSPS is violated, the semaphore is definitely obtained by one side or the other, but which side gets the semaphore is unpredictable.
Document #: 38-06078 Rev. *B
Page 11 of 18
[+] Feedback
Share Link: 
