CY8C20110-LDX2I View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
MFG CO.
'CY8C20110-LDX2I' PDF : 46 Pages View PDF
CY8C20110, CY8C20180
CY8C20160, CY8C20140
CY8C20142
AC GPIO Specifications
Table 11. 5-V and 3.3-V AC GPIO Specifications
Parameter
Description
Min
tRise0
Rise time, strong mode,
15
Cload = 50 pF, Port 0
tRise1
Rise time, strong mode,
15
Cload = 50 pF, Port 1
tFall
Fall time, strong mode,
10
Cload = 50 pF, all ports
Max Unit
Notes
80
ns VDD = 3.10 V to 3.6 V and 4.75 V to 5.25 V, 10%
to 90%
50
ns VDD = 3.10 V to 3.6 V, 10% to 90%
50
ns VDD = 3.10 V to 3.6 V and 4.75 V to 5.25 V, 10%
to 90%
Table 12. 2.7-V AC GPIO Specifications
Parameter
tRise0
tRise1
tFall
Description
Rise time, strong mode,
Cload = 50 pF, Port 0
Rise time, strong mode,
Cload = 50 pF, Port 1
Fall time, strong mode,
Cload = 50 pF
AC I2C Specifications
Table 13. AC I2C Specifications
Parameter
Description
FSCLI2C
SCL clock frequency
tHDSTAI2C
tLOWI2C
tHIGHI2C
tSUSTAI2C
tHDDATI2C
tSUDATI2C
tSUSTOI2C
tBUFI2C
tSPI2C
Hold time (repeated) START
condition. After this period, the
first clock pulse is generated
LOW period of the SCL clock
HIGH period of the SCL clock
Setup time for a repeated START
condition
Data hold time
Data setup time
Setup time for STOP condition
BUS free time between a STOP
and START condition
Pulse width of spikes suppressed
by the input filter
Min
Max
15
100
15
70
10
70
Standard Mode
Min
Max
0
100
4.0
–
4.7
–
4.0
–
4.7
–
0
–
250
–
4.0
–
4.7
–
–
–
Unit
Notes
ns VDD = 2.4 V to 2.90 V, 10% to 90%
ns VDD = 2.4 V to 2.90 V, 10% to 90%
ns VDD = 2.4 V to 2.90 V, 10% to 90%
Fast Mode
Min
Max
0
400
0.6
–
Units
Notes
kbps Fast mode not
supported for
VDD < 3.0 V.
µs
1.3
–
µs
0.6
–
µs
0.6
–
µs
0
–
µs
100
–
ns
0.6
–
µs
1.3
–
µs
0
50
ns
Document Number: 001-54606 Rev. *J
Page 27 of 46
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